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Semiconductor packaging part of integrated screened film and manufacture method thereof

A manufacturing method and semiconductor technology, which are applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, and semiconductor/solid-state device components, etc., can solve the problems of bulky semiconductor packages and the inability to effectively reduce the spacing of lead frames.

Active Publication Date: 2015-05-27
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, limited by the stamping method, the distance between two adjacent pins of the lead frame cannot be effectively reduced, resulting in an overly bulky semiconductor package
In addition, the influence of electromagnetic wave interference on semiconductor chips needs to be considered, but conventional lead frames cannot provide a design that prevents electromagnetic wave interference

Method used

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  • Semiconductor packaging part of integrated screened film and manufacture method thereof
  • Semiconductor packaging part of integrated screened film and manufacture method thereof
  • Semiconductor packaging part of integrated screened film and manufacture method thereof

Examples

Experimental program
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Embodiment Construction

[0053] Please refer to Figure 1A , which shows a cross-sectional view of a semiconductor package according to an embodiment of the present invention. The semiconductor package 100 includes a lead frame 110 , a first patterned pad layer 120 , a second patterned pad layer 130 , a chip 140 , a package body 150 , a shielding film 160 and a bonding wire 170 .

[0054] Such as Figure 1A As shown, the lead frame 110 has a plurality of first recesses 111 , a plurality of second recesses 112 , an outer surface 110s and an upper surface 110u and a lower surface 110b opposite to each other.

[0055] The first concave portion 111 extends from the upper surface 110u to the lower surface 110b , and the second concave portion 112 extends from the lower surface 110b to the first concave portion 111 to expose the package body 150 . In this embodiment, the first recessed portion 111 and the second recessed portion 112 are half-etched recesses, which do not penetrate the lead frame 110, but pe...

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PUM

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Abstract

The invention provides a semiconductor packaging part which comprises a lead frame, a first patterning cushion layer, a second patterning cushion layer, a chip, a packaging body and a screened film. The lead frame comprises a plurality of first depressed parts, a plurality of second depressed parts, an external side surface, an upper surface and a lower surface. The first depressed parts extend in a direction from the upper surface to the lower surface, and the second depressed parts extend to the first depressed parts from the lower surface. The first patterning cushion layer is formed on the upper surface of the lead frame and extends to the external side surface of the lead frame. The second patterning cushion layer is formed on the lower surface of the lead frame and extends to the external side surface of the lead frame. The chip is arranged in a corresponding first depressed part. The packaging body coats the chip and the first patterning cushion layer. The screened film covers an external surface of the packaging body, an external side surface of the first patterning cushion layer, the external side surface of the lead frame and an external side surface of the second patterning cushion layer.

Description

technical field [0001] The present invention relates to a semiconductor package with an integrated shielding film and a manufacturing method thereof, and more particularly to a semiconductor package with a patterned pad layer and a manufacturing method thereof. Background technique [0002] In the traditional lead frame, pins are formed by stamping method, and then the semiconductor chip is placed on the lead frame, and the lead angle of the semiconductor chip and the lead frame is connected by bonding wire or a suitable electrical connection method. [0003] However, limited by the punching method, the distance between two adjacent pins of the lead frame cannot be effectively reduced, resulting in an excessively large volume of the semiconductor package. In addition, the influence of electromagnetic wave interference on semiconductor chips needs to be considered, but conventional lead frames cannot provide a design that prevents electromagnetic wave interference. Contents...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/495H01L23/552H01L21/48H01L21/50
CPCH01L2924/0002H01L2224/73265H01L2924/00
Inventor 锺启生陈建成
Owner ADVANCED SEMICON ENG INC