Semiconductor device and method for fabricating same

Abstract

A method for fabricating a fine pattern of a semiconductor device is disclosed. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width is equal to the second width.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor component, in particular to using an advanced double-pattern process to manufacture a fine pattern of the semiconductor component. Background technique [0002] In order to integrate more components into a smaller area, the size of individual components needs to be reduced. In order to achieve a higher level of integration of semiconductor components, patterns must be miniaturized in the manufacture of semiconductor components. In recent years, the manufacturing technology of semiconductor devices has been continuously developed and improved to reduce the pitch of the pattern, which is the sum of the width of the basic feature of the pattern and the width of the gap between any two adjacent features. [0003] Lithography is one of the technologies currently used to manufacture highly integrated semiconductor components. In recent years, since the resolution achievable using lithography ...

AI Technical Summary

Problems solved by technology

However, spacers are typically not formed uniformly on each feature side, so it is difficult to control the CD and CD uniformity of fine patterns across a wafer using conventional dual patterning processes

Furthermore, in the conventional double patterning process, the spacers need to be removed after using the spacers as a hard mask, therefore, this conventional technique increases the number of required process steps and increases the manufacturing cost

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