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Multiphase frequency conversion circuit

A frequency conversion circuit and conversion circuit technology, applied in the direction of analog-to-digital converters, etc., can solve problems such as data transmission bottlenecks, inability to AD sampling signal processing, etc., and achieve the effect of solving down-conversion processing.

Inactive Publication Date: 2012-08-15
10TH RES INST OF CETC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method has the following disadvantages: due to the maximum effective operating rate of the digital device, when the AD sampling signal rate is much greater than the maximum effective operating rate of the digital device, there will be a data transmission bottleneck between the AD and the digital device, and the digital device will not be able to Normal processing of AD sampling signal

Method used

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Embodiment Construction

[0011] figure 1 In the described embodiment of the multi-phase frequency conversion circuit, the multi-phase frequency conversion circuit is sequentially composed of a serial-to-parallel conversion circuit, a multi-phase carrier generation circuit, multiple multipliers, multiple low-pass filters and an adder connected together.

[0012] Among them, at least two multipliers connected to the low-pass filter are connected between the serial-to-parallel conversion circuit and the adder, and the AD sampling digital signal is decomposed into multi-channel signals with multi-phase parallel output, and the M-channel AD samples after multi-phase decomposition The signal is multiplied with M channels of multiphase parallel local digital carrier signals respectively, and M channels of digital signals are obtained after multiplication, and the rate of each signal is 1 / M of the AD sampling rate, and at the same time, it is added by a connected adder to obtain the baseband The signal is do...

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Abstract

The invention relates to a multiphase frequency conversion circuit which comprises a serial-to-parallel conversion circuit, a multiphase carrier generation circuit, multipliers, low-pass filters and a summer, wherein the multipliers of at least two paths of connected low-pass filters are connected between the serial-to-parallel conversion circuit and the summer to decompose an AD (analog-to-digital) sampling digital signal into multiphase parallel output multi-channel signals, M channels of AD sampling signals after multiphase decomposition are respectively multiplied with M channels of multiphase parallel local digital carrier signals to obtain M channels of digital signals, and the rate of each channel of signals is 1 / M of an AD sampling rate, simultaneously, an additive operation is carried out therebetween by the connected summer so as to obtain a baseband signal, and then the baseband signal is down converted to a base band, wherein M is a natural number. According to the invention, a multiphase process is carried out on the AD-sampled digital signal and the local digital carrier, then the signal is decomposed into paralleled multi-channel signals, multiplied in parallel, filtered and added to realize the down conversion of the signal, therefore, the signal rate can be reduced and the problem that a high-speed signal sampled by high-speed AD cannot be subjected to the down conversion process in a digital device can be solved.

Description

[0001] technical field [0002] The invention relates to a multi-phase frequency conversion circuit mainly used for down-conversion of AD sampling digital signals. Background technique [0003] At present, the circuit for down-conversion of AD sampling digital signal adopts figure 2 The down-conversion circuit shown, the circuit first multiplies the AD sampling signal with the local digital carrier through the multiplier, converts the digital signal to the baseband, and then filters out its high-frequency components through a low-pass filter to extract the baseband signal. This method has the following disadvantages: due to the maximum effective operating rate of the digital device, when the AD sampling signal rate is much greater than the maximum effective operating rate of the digital device, there will be a data transmission bottleneck between the AD and the digital device, and the digital device will not be able to Perform normal processing on the AD sampling signal. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/60
Inventor 黄凌扈景召曾力
Owner 10TH RES INST OF CETC