Memory array and associated manufacturing method

Abstract

Memory arrays and associated fabrication methods are disclosed herein. In one embodiment, a memory array includes access lines extending in a first direction and first and second contact lines extending in a second direction different from the first direction. The first and second contact lines are generally parallel to each other. The memory array also includes a memory node including a first memory cell electrically connected between the access line and the first contact line to form a first circuit, and electrically connected to the access line line and the second contact line to form a second memory cell of a second circuit different from the first circuit.

Description

technical field [0001] The present technology is generally directed to memory arrays and associated fabrication methods. Background technique [0002] Memory cells, such as floating gate transistors or PCRAM cells, are typically arranged in an array connected to a grid formed of a plurality of word and bit lines. The word lines are generally parallel to each other and perpendicular to the bit lines. Each of the memory cells forms a node of the array, and each node is connected to a particular pair of word and bit lines. In operation, each memory cell can be accessed individually by energizing a particular pair of word and bit lines while floating or oppositely biasing the remaining word and bit lines. [0003] However, conventional arrangements of such memory arrays cannot accommodate more than one memory cell per node. If the memory array includes two memory cells per node that are connected to a pair of word lines and bit lines, then energizing the pair of word lines an...

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Problems solved by technology

Therefore, the two memory cells may not be individually addressed or accessed

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