Positioning structure of semi-conductor chip cantilever package

Abstract

The invention relates to a positioning structure of a semi-conductor chip cantilever package, comprising upper formworks and lower formworks which are arranged in a vertical direction at intervals; upper modules and lower modules are arranged between the upper formworks and the lower formworks; the structure is characterized in that in the upper modules, upper templates are positioned relative to the upper formworks; first turn-in plates and second turn-in plates are movably arranged in the vertical direction relative to the upper formworks; the first turn-in plates are towards the upper templates and are provided with upper module thimbles corresponding to plastic rubber bodies, and the second turn-in plates are towards the upper templates and are provided with upper module clamping thimbles corresponding to semi-conductor chip cantilevers; in the lower modules, the lower templates are positioned relative to the lower formworks; third turn-in plates and fourth turn-in plates are movably arranged in the vertical direction relative to the lower formworks; the third turn-in plates are towards the lower templates and are provided with lower module thimbles corresponding to the plastic rubber bodies, and the fourth turn-in plates are towards the lower templates and are provided with lower module clamping thimbles corresponding to the semi-conductor chip cantilevers; and the positioning structure solves the positioning problem of bare chip components in the Z direction of a cantilever end in a die cavity.

Description

technical field [0001] The invention relates to the technical field of packaging of semiconductor devices, and particularly designs a positioning method for cantilever packaging of semiconductor chips. Background technique [0002] The packaging of semiconductor electronic components not only plays the role of connecting the internal semiconductor chip with the external electrical components, but also plays the role of mechanical protection and environmental sealing. Therefore, the quality of packaging is closely related to the overall performance of semiconductor devices. [0003] There are various packaging methods for semiconductor devices, among which there is a packaging method suitable for ordinary semiconductor devices, that is, injection molding. This method usually uses epoxy resin as the packaging material, and forms a cavity through pressure clamping of the upper and lower molds, while the bare chip component is positioned in the center of the cavity, and then pr...

AI Technical Summary

Problems solved by technology

It is conceivable that if a bare chip assembly has front-to-back or left-right bidirectional pins, the mold will press the pins from both ends to easily position the bare chip in the X, Y, and Z directions of the cavity; but if a bare chip assembly has only one side single The positioning of the direction pins in the cavity will be in a cantilever state. In this state, the positioning of the bare chip component relative to the cavity space in the X and Y directions can be controlled by the cooperation of the pins and the mold, but the positioning in the Z direction depends on the Difficult to control with increased arm length

Especially for thin or flat semiconductor devices, not only the positioning in the Z direction is very necessary but also the control is very difficult

Therefore, if the position of a bare chip component in the Z direction in the cavity cannot be fixed, the distance from the chip to the surface of the body in the Z direction cannot be controlled. If the distance from the surface is too close, the insulation and voltage resistance of the device will be poor, which will directly affect the product quality. and pass rate

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