A kind of access control method and system and main control board
A technology of access control and normal access, which is applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problems of easy misoperation, additional software configuration, equipment complexity, etc., and achieve the effect of hot swapping and eliminating abnormal phenomena
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Embodiment 1
[0061] The application scenarios used in this embodiment are as follows:
[0062] The central processing unit (CPU) of the main control board sends a chip selection signal, and the response signal of the accessed chip to the chip selection signal is a TA signal, which indicates the response of the completion of data transmission. For the CPU, the time it takes for one access is the period from when the CPU sends the chip select signal to when it receives the TA signal fed back from the chip being accessed, which is commonly referred to as the normal access cycle. in:
[0063] figure 2 It is a sequence diagram of normal CPU access in the application scenario of Embodiment 1 of the present invention;
[0064] It can be seen from the figure that in this application scenario, the chip selection signal is valid when it is at a low level, and on the contrary, it is invalid when the chip selection signal is at a high level. The TA signal is valid when it is low level, on the cont...
Embodiment 2
[0084] Figure 5 It is a sequence diagram of normal CPU access in the application scenario of Embodiment 2 of the present invention.
[0085] exist Figure 5 In the timing diagram shown, the CPU sends a chip select signal, and the chip outputs a response signal READY signal after receiving the chip select signal, where the pulse of the READY signal is a negative pulse, and the CPU samples the negative pulse to obtain the nEWAIT signal, End this visit.
[0086] Figure 6 It is a sequence diagram when the service board is pulled out during the CPU read or write operation to the chip in the application scenario of the second embodiment of the present invention.
[0087] through with Figure 5 It can be seen from the comparison that after being pulled out, the interface that outputs the READY signal is in a floating state and maintains a certain value of current, so the READY signal is always at a low level, so there is no Figure 5 In the case of the negative pulse shown, th...
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