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Memory access controller supporting data descrambling and memory access controller descrambling method

A controller and data technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of inconvenient large-scale data processing, small parallelism, simplicity, etc., and achieve the effect of improving data processing capabilities

Active Publication Date: 2016-05-18
北京中科晶上科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If separate hardware is used to realize the data descrambling function, it will not only increase the chip area, but also increase the difficulty of control (especially for real-time data streams)
In addition, in the existing hardware implementation, the serial descrambling method is simple and inefficient; the parallel descrambling method has only a small degree of parallelism, which is not convenient for large-scale data processing; if the software method is used to realize the data descrambling features, which take up valuable processor resources

Method used

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  • Memory access controller supporting data descrambling and memory access controller descrambling method
  • Memory access controller supporting data descrambling and memory access controller descrambling method
  • Memory access controller supporting data descrambling and memory access controller descrambling method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0044] like figure 1 As shown, the memory access controller is provided with three descrambling channels and an arbiter, and the arbiter is located after the three descrambling channels. Wherein; the three descrambling channels perform corresponding descrambling on different types of source data according to the control instructions of the memory access controller; the arbiter judges the data obtained after descrambling to output the corresponding data .

[0045] The execution process is as follows: when the state controller in the memory access controller issues a data transmission start command, it will automatically obtain the valid data to be descrambled from the memory, and transfer it to the three descrambling channels, and then in the descrambling channel according to the DMA The DMA information stored in the register group and the control information stored in the data descrambling register group are descrambled for the valid data to be descrambled. When the valid da...

Embodiment 2

[0049] like figure 2As shown, the memory access controller is provided with three descrambling channels, one direct channel and three arbiters, wherein the three descrambling channels respond to different types of source data according to the control instructions of the memory access controller descrambling; direct channel, carrying non-descrambling data; three arbiters including a first arbiter, a second arbiter and a third arbiter, wherein;

[0050] The first arbiter judges the source data according to the control instruction of the memory access controller, so as to distinguish the descrambled data and the non-descrambled data;

[0051] The second arbiter judges the data to be descrambled according to the control instruction of the memory access controller, so as to distinguish different types of data and assign each descrambling channel for descrambling;

[0052] The third arbiter judges the data obtained after descrambling and the non-descrambling data according to the ...

Embodiment 3

[0062] Example 3: Generating polynomial x for scrambling code 15 +x 14 +1, the specific production process is: in the process of DMA moving and data descrambling at the same time, the scrambling code sequence can be as follows: image 3 The cyclic shift register shown is generated.

[0063] 1. Initialize the control word, including the initial value (X) of the 16-bit register as shown in the figure, the calculation length of the scrambling code preparation sequence, etc.

[0064] 2. Start DMA to obtain data from the data source,

[0065] 3. Use the generated scrambling code sequence to descramble the data,

[0066] 4. The processed data is stored in the storage unit.

[0067] The scrambling code is generated as follows:

[0068] X[1] <= X[0];

[0069] X[2] <= X[1];

[0070] X[14] <= X[13];

[0071] X[0]<=X[14]^X[13].

[0072] Each clock cycle generates a scrambling code, that is, the value of X[13]^X[14].

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Abstract

The invention discloses an accessing storing controller capable of supporting data descrambling, which is provided with at least one descrambling channel with a data descrambling function and at least one arbitrator for judging and selecting data. A descrambling method for the accessing storing controller comprises the following steps: obtaining an operation data from a data source and sending a control instruction; performing data descrambling on the operation data in the descrambling channel in the accessing storing controller according to the control instruction; and after finishing the descrambling, outputting the data after being descrambled and storing. According to the accessing storing controller, the descrambling channel with the data descrambling function is arranged in the accessing storing controller, the data transmission can be finished and the data descrambling treatment also can be finished under the combined action of the descrambling channel and the other element in the accessing storing controller, so that the data handling capacity of the accessing storing controller is increased. A plurality of descrambling channels are defined, the selective independent descrambling for different data signals is finished, and each of the descrambling channels can support a use mode of a descrambling sequence.

Description

technical field [0001] The present invention relates to the technical field of memory access control, in particular to a memory access controller supporting data descrambling and a memory access controller descrambling method. Background technique [0002] At present, for batch data (data stream) processing, the main memory access control mechanism is DMA (Direct Memory Access, direct memory access) technology, and the DMA technology is suitable for the memory access control technology of batch data processing. After the general processor (or other controller) hands over the memory access task of batch data to the DMA, the DMA accepts the task and performs the memory access operation, and returns a task completion control signal to the processor (or other controller) after the task is completed. [0003] The existing memory access control DMA technology only realizes data transmission control, and data processing is completed by software or hardware alone after data transmis...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/30
Inventor 石晶林朱子元刘金宝黄守俊冯雪林
Owner 北京中科晶上科技股份有限公司
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