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Method for simulating low speed parallel interface by using GPIO (general purpose input output)

An interface and low-speed technology, which is applied in the field of using GPIO to simulate low-speed parallel interfaces, can solve problems such as the inability to find conversion chips

Active Publication Date: 2013-01-16
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Generally speaking, replacing the interface conversion chip and using a new interface conversion chip to convert the low-speed parallel interface of the core unit into a PCIe slave interface can meet such upgrade needs, but no conversion chip with this function can be found in the market. Only conversion chips such as GPIO (General Purpose Input Output, general purpose input / output) converted from the PCIe slave interface can be found. The chip provides multiple control registers to realize the control of GPIO

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  • Method for simulating low speed parallel interface by using GPIO (general purpose input output)

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Embodiment Construction

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0043] In the embodiment of the present invention, select PCIe bridge chip XR17V352IB113-F to design, this chip has PCIe slave interface, has 16 GPIOs, is GPIO[0] to GPIO[15] respectively, connects GPIO[0] to GPIO[15]. GPIO[3] is defined as a control signal pin, respectively: GPIO[0] is defined as its own buffer state output pin, GPIO[1] is defined as the other party’s read signal input pin, and GPIO[2] is defined as the other party’s buffer state input pin Pi...

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Abstract

The invention discloses a method for simulating a low speed parallel interface by using GPIO (general purpose input output). The method comprises the following steps of: dividing a GPIO pin of an interface conversion chip into a data pin and a control pin; defining the data pin as a data bus of the low-speed parallel interface; defining the control pin as a control bus of the low-speed parallel interface; controlling a GPIO data register and an input / output control register inside the interface conversion chip through a GPIO control module in a driving program of the interface through PCI e (periphery component interconnect express), so as to enable the data bus and the control bus to be at a working operation state of the low speed parallel interface.

Description

technical field [0001] The invention relates to the field of tax control, in particular to a method for simulating a low-speed parallel interface by using GPIO. Background technique [0002] Existing special hardware equipment for tax control, because of the continuation of the product, its core unit only has a low-speed parallel interface, and the low-speed parallel interface is transferred to a PCI slave interface through a conversion chip from a parallel port to a PCI (Peripheral Component Interconnect) interface , the transferred PCI slave interface is used as the overall external communication interface of the tax control equipment. When in use, the tax control equipment is installed on the PCI expansion slot of the microcomputer. [0003] With the development of computer bus technology, the expansion slot of the microcomputer will be replaced by PCIe (Peripheral Component Interconnect Express), so the PCI slave interface of the tax control equipment also needs to be up...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
Inventor 甘景全崔志民宋晓林贺毅王招凯洪岩
Owner AEROSPACE INFORMATION
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