63 results about "General-purpose input/output" patented technology

The invention discloses an automatic test-oriented communication protocol and sequential logic cooperative control system, and relates to the technical field of nuclear field instrument and control system test, and the system comprises a 7-slot computer cage, a controller, a function card, a dual-path full duplex communication link, and a power supply monitoring module. The controller is fixed at the slot 0 of the 7-slot cage, and the function card is inserted in the slot 1 to the slot 6 in a mixed manner. And the controller is connected with each function card through a double-path full duplex communication link, is linked with the power supply monitoring module through a GPIO (General Purpose Input / Output) signal so as to monitor and control the power supply of the function card, and is also connected with the HMI through a gigabit Ethernet. The controller receives a test case of the HMI based on a first preset communication protocol, generates a test instruction, packages the test instruction into a control frame through a second preset communication protocol, issues the control frame according to three time sequence regulation and control modes, receives the state and test data returned by the function card, and intervenes the abnormal function card through the power supply monitoring module. And the function card analyzes the instruction, executes a test, collects and returns data, and reports the operation state at the same time.

The invention relates to a GPIO (General Purpose Input / Output) input anti-shake method for a domestic PLC (Programmable Logic Controller), and relates to the technical field of industrial automation. The method comprises the following steps: configuring an anti-shake structural body for each GPIO channel; and for each GPIO channel, if the state flag of the GPIO channel is an uninitialized state, carrying out initialization sampling for a preset number of times according to a preset stable waiting time interval. And setting a state flag and a current sampling value according to an initialized sampling result. And for each GPIO channel, if the state flag of the GPIO channel is a stable state or a filtering starting state, periodically sampling a GPIO input signal based on a timing interruption mechanism and a preset interruption period. And updating a state flag and a current sampling value according to a periodic sampling result on the basis of a stable frequency threshold value of the GPIO channel. And if the state flag of the GPIO channel is a stable state, updating the stable value of the GPIO channel to the current sampling value. According to the invention, the signal stable acquisition capability and the overall reliability of the PLC in an industrial interference environment can be improved.

An electronic device is provided. The electronic device includes a battery, a power management module, a charging circuit, and a processor including a central processing unit (CPU) and a plurality of intellectual property (IP) blocks. The charging circuit is connected to the processor and includes a first pin to output a first overcurrent warning signal. The power management module is connected to the processor and includes a second pin to output a reset warning signal. The processor includes a first general purpose input output (GPIO) pin to receive the first overcurrent warning signal, and is configured to reduce at least one clock frequency among a plurality of clock frequencies set to each of the CPU and the plurality of IP blocks, or reduce at least one operation clock frequency of components inside the electronic device when the first overcurrent warning signal is received through the first GPIO pin.

The present invention relates to a device and a system for debugging a solid state disk device, the device comprising: a joint test action group add-on board; and a Raspberry Pi. The Raspberry Pi comprises a general purpose input output interface coupled to the joint test action group add-on board; and a processing unit coupled to the general purpose input output interface. The processing unit is configured to emulate a plurality of joint test action group commands to the solid state disk device through the general purpose input output interface to dump data generated by the solid state disk device during runtime of the solid state disk device. Using the device as described above can reduce the cost required to debug the solid state disk device.

A system and method for automatically detecting a type of memory card inserted into a portable computing device. The system may include a system on chip capable of detecting a first type of memory card and a second type of memory card. For this detection, the system on chip does not have / does not use an analog switch. The first memory card may be a secure digital express memory card. Meanwhile, the second memory card may be a secure digital memory card. The system on chip may include a general purpose input / output pin. The general purpose input / output pin may activate a first communication bus protocol associated with the secure digital express memory card in response to receiving a first signal. The first signal may be generated by a reserved for future use pin on the first type of memory card.

The invention discloses an intelligent decorative lighting control circuit and an intelligent lamp. The intelligent decorative lighting control circuit comprises a main control chip, a storage chip, a power amplifier chip, a key circuit, an infrared receiving circuit, an audio input circuit, an MOS tube driving circuit and a step-down conversion circuit, the main control chip is connected with the storage chip through an SPI (Serial Peripheral Interface), is connected with the input end of the power amplifier chip through a DAC (Digital-to-Analog Converter) output pin, and is respectively connected with the key circuit, the infrared receiving circuit, the audio input circuit and the MOS tube driving circuit through GPIO (General Purpose Input / Output) pins; the input end of the step-down conversion circuit is connected with an external direct-current power supply, and the output end is respectively connected with power supply pins of the main control chip, the storage chip and the power amplifier chip; and the main control chip reads audio data in the storage chip according to an input signal of the key circuit or the infrared receiving circuit and outputs the audio data to the power amplifier chip, or generates a PWM control signal and outputs the PWM control signal to the MOS tube driving circuit so as to perform intelligent cooperative control on the lamp. According to the invention, the system hardware complexity and cost are reduced.

This application provides a communication method, apparatus, medium, and system for a general-purpose input / output port. The method includes: a first device determining first communication information to be sent and querying a first mapping table to determine a first duty cycle corresponding to the first communication information; encoding the first communication information into a first pulse signal according to the first duty cycle; sending the first pulse signal to a second device; and the second device sending a second pulse signal to the first device, wherein the second pulse signal is obtained by the second device encoding the second communication information according to a second duty cycle corresponding to the second communication information to be sent. Embodiments of this application encode information using different duty cycles, thereby achieving differentiation between multiple instructions and multiple states. This application can solve the problems that general-purpose input / output ports cannot differentiate information or encode multiple instructions and multiple states, enabling general-purpose input / output ports to support bidirectional, multi-instruction, and multi-state data interaction.

The utility model discloses a communication board card and an LCU (Local Control Unit) case comprising the communication board card, particularly relates to the technical field of communication equipment, and is technically characterized in that the communication board card comprises a plurality of communication devices, and each communication device comprises a control processor; the first communication equipment, the second communication equipment and the third communication equipment are connected with the control processor; each of the plurality of control processors is provided with a GPIO (General Purpose Input / Output) input port and a GPIO output port, and the plurality of control processors are mutually connected through the GPIO input ports and the GPIO output ports; the plurality of first communication devices are connected with an upper computer, the plurality of second communication devices are connected with a first external communication bus, and the plurality of third communication devices are connected with a second external communication bus.

The utility model relates to the technical field of LED control circuits, in particular to an LED display state control circuit. The control circuit comprises a main chip used for generating a control signal; the plurality of GP IO ports are arranged on the main chip and are used for outputting the control signals; and the LED control circuit is electrically connected with the GPIO ports, receives the control signal and adjusts the on-off state of an LED according to the control signal. The LED display state control circuit provided by the utility model is more flexible. By using a mode of combining a plurality of GPIO (General Purpose Input / Output) ports with an NPN (Negative-Positive-Negative) triode, independent control on a plurality of LEDs is realized. Specifically, the main chip outputs control signals through a plurality of GP IO ports, and the signals are transmitted to each LED through an NPN triode, so that the on-off state of each LED can be flexibly controlled. The expansibility of the system is improved, and the information displayed by the LED is richer and more diversified.

The invention belongs to the technical field of communication, and relates to a method, a device and equipment for configuring a communication protocol at a slave end and a storage medium, at least two GPIO (General Purpose Input / Output) interfaces of a communication interface of a slave are used as detection ports, and the method for configuring the communication protocol at the slave end comprises the following steps: enabling the slave to enter a power-on state, and setting the communication interface to be in an input mode; reading the levels of all the detection ports; comparing the read levels of all the detection ports with pre-stored level truth value information, wherein the level truth value information comprises the levels of all the detection ports of which the communication interfaces are connected with hosts adopting SPI, UART and I2C communication protocols respectively and which are in an idle state; identifying a communication protocol type currently adopted by the host according to a comparison result; the communication interface is configured to support the identified communication protocol type. According to the technical scheme adopted by the invention, the slave computer can support the SPI, UART and I2C communication protocols without designing a plurality of groups of communication interfaces or carrying out model design on various communication protocols.

The utility model provides a general purpose input / output (GPIO) pin compatibility testing device, which comprises a Cat.1 communication module and a plurality of resistors, the Cat.1 communication module is provided with a plurality of groups of input pins and a plurality of groups of output pins, and the plurality of resistors are connected between the input pins and the output pins in the plurality of groups of input pins and the plurality of output pins; according to different connections between the input pin and the output pin, changing the pin state of the input pin or the output pin through an instruction of the Cat.1 module; therefore, different GPIO test schemes can be selected according to different GPIOs, the design and development cost is reduced, the automatic production line changing time is shortened, the construction of a production test environment is facilitated, the compatibility of a test tool is improved, and the cost of a test fixture is saved.

The utility model relates to the technical field of circuits, in particular to a motor self-adjusting control circuit and a stamper machine, and the motor self-adjusting control circuit comprises a single-chip microcomputer, an infrared geminate transistor, a stamper motor driving chip and a two-phase stepping motor. A first UART (Universal Asynchronous Receiver / Transmitter) interface of the singlechip is connected with an infrared geminate transistor, a first GPIO (General Purpose Input / Output) interface of the singlechip is connected with an input end of a seal motor driving chip, an output end of the seal motor driving chip is connected with a two-phase stepping motor, and the two-phase stepping motor is connected with one end of a seal; infrared photoelectric signals are detected through the infrared geminate transistors, pulse signals are output to the seal motor driving chip after the single-chip microcomputer receives the infrared photoelectric signals fed back by the infrared geminate transistors, and the rotation angle of the two-phase stepping motor is controlled through the seal motor driving chip, so that the number of rotation turns of the lead screw in the two-phase stepping motor is adjusted, and the seal is achieved. The purpose of controlling the height of the seal is achieved.

A system and method of transmitting signals are provided. The method includes: acquiring a Virtual Pin Port (VPP) lighting signal and a Serial General Purpose Input / Output (SGPIO) lighting signal by a server motherboard, a hard disk backplane being deployed with a target logic device and a set of hard disk slots; and scheduling and switching the VPP lighting signal and the SGPIO lighting signal in an orderly time-division way by using a preset time-division multiplexing manner, so as to transmit the VPP lighting signal and the SGPIO lighting signal to the target logic device through a same lighting cable.

The invention belongs to the field of relay training, and discloses a relay multi-sensory feedback intelligent auxiliary system, and the system comprises a real-time speed detection system based on UWB, which is used for achieving the precise calculation of the position of an athlete, calculating the speed of the athlete in real time through a bilateral distance measurement method, and feeding back the speed to a coach; the visual signal feedback device is a flexible LED lamp strip arranged in a range from 15 m in front of the relay area to 5 m in the relay area, and is provided with a high-brightness protective structure; the tactile signal feedback device is integrated with a vibration motor of an LRA linear resonance actuator, and controls vibration through a GPIO (General Purpose Input / Output) pin; and the hearing signal feedback device is a small loudspeaker or a buzzer integrated on the bracelet or the shoulder. The real-time speed of the athlete at each moment in the relay process is obtained, the optimal handover time and the relative optimal handover position of the athlete are calculated, and multi-sensory feedback is realized through tactile, visual and auditory signals, so that intelligent assistance is realized in the rod handover process, and the rod handover accuracy is improved. And the training efficiency and the competition stability are improved.

The invention relates to the field of embedded resource management, and discloses a GPIO (General Purpose Input / Output) resource management method, GPIO resource management equipment and a storage medium. The method comprises the following steps: creating a GPIO directory file in a Linux application system; creating a GPIO interface file in the GPIO directory file; the method comprises the following steps: creating a GPIOs subdirectory file in a Linux kernel system, and placing a GPIO interface file in the GPIOs subdirectory file; analyzing GPIO description information in the preset device tree source file; according to the GPIO description information, generating a GPIO configuration interface, and sending a GPIO resource request to the Linux kernel; obtaining resource parameters based on the GPIO resource request; and creating a GPIO interface instance file in the Linux application system. In the embodiment of the invention, through interface file control and management, unified management and dynamic configuration of GPIO resources are realized, and code redundancy is remarkably reduced.

The invention discloses a Flash starting system and method based on a trusted measurement mechanism. The Flash starting system and method are suitable for starting scenes of main and standby Flash memories of domestic CPUs (central processing units). The system comprises a domestic CPU (central processing unit), a CPLD (complex programmable logic device), a TPCM (trusted platform control module), a main Flash memory, at least one standby Flash memory and a GPIO (general purpose input / output) signal line. And the CPLD expands a single-path SPI interface of the CPU into multiple paths through logic programming, and is connected with the main Flash and the standby Flash to realize intelligent switching. The TPCM performs trusted measurement on the boot firmware of the main and standby Flash memories after the system is powered on, so that the integrity of the boot firmware is ensured. And during starting, loading is preferentially carried out from the main Flash memory, and if the loading fails, the standby Flash memory is automatically switched to, so that the starting reliability and stability of the system are improved. Through combination of hardware redundancy and trusted measurement, malicious starting of firmware loading is effectively prevented, and safe and stable operation of the system is guaranteed.

The systems and procedures described herein correspond to power harvesting operations. The power management switching logic (170) can receive a supply voltage from another power management switching logic (152). This supply voltage can be a harvested supply from the other power management switching logic (152). Furthermore, part of the power management switching logic (152) can be operated as a controller power management switching logic (152) to supply the voltage via one or more rails, and part of the power management switching logic (170) can be operated as a leaf power management switching logic (170) to harvest the supply voltage from one or more rails.The leaf power management switching logic (170) can exclude a controller (156), thereby enabling this leaf power management switching logic (170) to be placed in a lower power mode than was previously possible when the controller (156) was included.

The invention relates to a self-management low-power-consumption sleep and wake-up exception handling method based on an Android system, and the method comprises the following steps: a kernel power management module is created in a kernel layer, the kernel power management module is used for detecting the power state of the Android system and starting a power management service program, and the power state comprises a sleep state, a wake-up signal and a heartbeat signal; the kernel power management module detects dormancy and wake-up signals through a GPIO (General Purpose Input / Output) state; when the ACC signal is turned to off, the power management service program starts the system to sleep; when the ACC signal becomes on, the power management service program wakes up the system and recovers heartbeat detection; and if the heartbeat signal is not received within the specified time, the power management service program actively restarts the Android system. According to the method, the problem of dependence of the MCU in the prior art is solved, and meanwhile, the flexibility and reliability of the system are improved.

The present invention relates to a hard macro interface which controls transmission and reception of test signals between a hard macro block and general purpose input / output (GPIO) in a system-on-chip in a test mode so that a test for the general purpose input / output (GPIO) can be performed, and a system-on-chip comprising same. The hard macro interface according to the present disclosure comprises: at least one hard macro interface unit configured to correspond to each of a plurality of ports constituting a hard macro block and configured to provide port input / output to a corresponding port according to a test mode type; and a test controller configured to output predetermined register test data to the at least one hard macro interface unit, wherein the port input / output includes at least one among pad test input / output of a GPIO pad and the register test data.

The invention relates to the technical field of industrial communication networks, in particular to a rapid message forwarding method from a GPIO (General Purpose Input / Output) interface to a WIA-FA (Wireless Interface Architecture-FA) interface, which comprises the following steps of: directly connecting the GPIO interface and the WIA interface by adopting a hardware forwarding module, and executing the whole process of message receiving, interface type judgment, data field extraction, protocol configuration information reading, WIA header construction, message packaging and sending through hardware. Context switching and memory copying of a software protocol stack are avoided; and the hardware forwarding module automatically selects a forwarding path from GPIO to WIA or from WIA to GPIO according to a message source, so that full-link hardware processing is realized, the transmission delay is remarkably reduced, the message forwarding efficiency is improved, and real-time reliable communication between equipment in an industrial automation environment is supported.

Techniques for chip-to-chip (C2C) serial communication, such as communication between chiplets on a multi-chip package, are disclosed. In some aspects, a method of monitoring on a die of a C2C link includes detecting a change of the C2C link from a first link state to a second link state, and storing link state change information in a first-in-first-out (FIFO) buffer on the die. The link state change information indicates the first link state, a duration of time that the C2C link was in the first link state, and a speed of the C2C link in the first link state. Upon detecting a request for the link state change information, the link state change information is retrieved from the FIFO buffer and sent in a serial fashion to an output pin of the die, such as a general purpose input / output (GPIO) pin.

The invention provides a server fan control system and method, a server BMC (Baseboard Management Controller) respectively controls the working states of a gating switch and a change-over switch through a GPIO (General Purpose Input / Output) interface, so that when the gating switch is switched off and the change-over switch enables a CPLD (Complex Programmable Logic Device) to communicate with the fan, the CPLD sends a first PWM (Pulse Width Modulation) control signal to the fan to control the rotating speed of the fan; when the gating switch is conducted and the change-over switch enables the PWM signal generation unit to communicate with the fan, the CPLD sends PWM control data to the PWM signal generation unit so that the PWM signal generation unit can send a second PWM control signal to the fan based on the PWM control data to control the rotating speed of the fan, and even if CPLD firmware upgrading needs to be carried out, the rotating speed of the fan can still be controlled through the PWM control signal. Therefore, electronic components in the server are prevented from being overheated and damaged due to the fact that the fan does not work when the CPLD firmware is upgraded.

The application belongs to the technical field of integrated circuits and provides a general input and output interface circuit and a system on chip, which comprises a core voltage detection module and an IO voltage power-on detection module, and a first level shift module, a third level shift module and a first pre-driver module are connected in series between an internal control module and a PMOS tube module; a second level shift module and a second pre-driver module are connected in series between the internal control module and an NMOS tube module; a first bias end of a voltage bias module is connected to the IO voltage power-on detection module, the third level shift module, the first pre-driver module and the PMOS tube module; a second bias end is connected to the first level shift module, the core voltage detection module, the second level shift module, the second pre-driver module and the NMOS tube module, and the core voltage detection module is further connected to the first level shift module and the second level shift module. In the embodiment of the application, no burr is generated in PAD output, and the complexity of circuit design is reduced.

The embodiment of the utility model discloses a control panel, a server mainboard control system and a server. The control panel comprises a microcontroller unit, a connector and a voltage conversion unit, the microcontroller unit is connected with the connector through a plurality of general input / output port buses, and is also connected with the connector through a modular peripheral sideband tunnel interface bus and a detection line; the voltage conversion unit is connected with the microcontroller unit; the connector is used for connecting a mainboard; the microcontroller unit is used for carrying out data transmission with a mainboard through the modular peripheral sideband tunnel interface bus when detecting a low level signal of the detection line, and is also used for carrying out data transmission with the mainboard through a plurality of universal input / output port buses when detecting a high level signal of the detection line. The single board of the control board provided by the embodiment of the utility model is butted with a server mainboard supporting an M-PESTI protocol and a GPIO (General Purpose Input / Output) interface, so that multiple purposes of one card are realized.

The invention provides a method for realizing multiple functions based on a single GPIO (General Purpose Input / Output), a storage medium and a signal transmission structure. The method for realizing multiple functions based on the single GPIO comprises the following steps: receiving an instruction signal output by a sending end; calculating a preset number of frequency values of the instruction signal in a preset duration; if the occurrence frequency of one instruction signal frequency value is greater than or equal to a frequency threshold value corresponding to the instruction signal frequency value, determining a function corresponding to the instruction signal frequency value based on a preset mapping relation; and triggering a function corresponding to the instruction signal frequency value. By analyzing the frequency value of the instruction signal, the function corresponding to the frequency value is determined and executed. And the frequency value of the instruction signal is allowed to be changed on one GPIO line, so that the receiving end can realize different functions.

The invention discloses a batch online upgrading system and method for an FPGA, relates to the technical field of online upgrading, and mainly aims at solving the problems that an existing FPGA upgrading mode is tedious in operation, low in efficiency and high in cost. The system comprises an upper computer, a plurality of microcontrollers and distributed FPGA equipment; when online upgrading is processed, the upper computer carries out subpackage processing on the FPGA program to be upgraded to obtain a plurality of data packets; the upper computer sends the plurality of data packets to each microcontroller through a UART bus, so that each microcontroller stores each data packet; and each microcontroller carries out verification processing on each received data packet and feeds back a verification result to the upper computer. When the verification result received by the upper computer is that the verification is successful, indicating each microcontroller to perform JTAG (Joint Test Action Group) simulation; and each microcontroller uses a GPIO (General Purpose Input / Output) pin to simulate a JATG protocol to upgrade the distributed FPGA equipment.

The invention relates to a double-direct-current brushless motor speed closed-loop control system and method, and the system comprises a digital signal processor which comprises an ePWM module and a GPIO channel, the ePWM module is used for generating a PWM control signal, and the GPIO channel is used for receiving a Hall sensor signal; the isolation circuit is used for amplifying the PWM control signal and then driving the three-phase full-bridge inverter circuit; the three-phase full-bridge inverter circuit is respectively connected with the isolation circuit and the direct-current brushless motor and is used for controlling the power-on state of a motor winding according to the PWM control signal so as to control the direct-current brushless motor; the Hall sensor is arranged on a stator of the direct current brushless motor and outputs three paths of Hall position signals to a GPIO (General Purpose Input / Output) channel of the digital signal processor; and the digital signal processor realizes independent speed closed-loop control on the plurality of direct-current brushless motors by adjusting PWM control signals based on the three paths of Hall position signals and rotating speed feedback. According to the invention, the cooperative control reliability under complex working conditions can be enhanced.

The invention discloses a multi-module redundancy mode control method without quick communication. The method comprises the following steps: initializing a GPIO (General Purpose Input / Output) port of each module in a modular three-level grid-connected rectifier; after the initialization is completed, numbering each module through a master control unit, and distributing an operation state for each module; when any module breaks down, state switching is triggered through level jump of the GPIO port, and redundant standby is achieved; the master control unit reorders the numbers of all the current modules according to the fault condition, and redistributes the working state of each module; and after the distribution is completed, the fault module is replaced, and meanwhile, the system is recovered to a redundancy preparation state. On the premise that the hardware cost is not increased, the fluctuation of the output voltage of the parallel direct-current power supply system caused by the fault of a single module can be remarkably reduced, the problem of system instability caused by the fault of a traditional master-slave mode host is solved, and the method is of great significance to stable operation of a high-capacity and high-reliability power supply.

The invention discloses an equipment reading method, device and equipment, which are applied to a system comprising a single GPIO (General Purpose Input / Output) port and an SOC (System On Chip) bus, the system is connected with external equipment through the GPIO port and the SOC bus, and the method comprises the following steps: reading a GPIO state value of the GPIO port; reading equipment information of external equipment through the SOC bus; and sending the GPIO state value and the equipment information to the kernel through the cmdline, analyzing the GPIO state value and the equipment information by the kernel, and determining the version information of the external equipment. According to the invention, only one GPIO port and the SOC bus are needed to identify the version information used for reflecting the hardware versions of different external devices, and a plurality of GPIO ports do not need to distinguish different external devices, so that the limitation caused by the fact that the hardware versions of different external devices cannot be effectively identified due to limited GPIO port resources in the prior art is solved.

Systems and methods described herein correspond to power supply acquisition operations. The power management circuit (170) may receive a supply voltage from other power management circuits (152). The supply voltage may be a supply drawn from other power management circuitry (152). Further, some of the power management circuits (152) may operate as a controller power management circuit (152) to supply the supply voltage via the one or more rails, and some of the power management circuits (170) may operate as a leaf power management circuit (170) to draw the supply voltage from the one or more rails. The leaf power management circuit (170) may not include a regulator (156), thereby enabling the leaf power management circuit (170) to enter a mode of lower power than previously enabled when including the regulator (156).