155 results about "General-purpose input/output" patented technology

The invention discloses a server mainboard, a server, a bandwidth acquisition method, a product, equipment and a medium, and relates to the technical field of server interface control, the server mainboard comprises a bandwidth allocation identification component arranged for a bus equipment slot, the bandwidth allocation identification component can identify the bandwidth allocation condition of the corresponding bus equipment slot, and the bandwidth allocation condition of the corresponding bus equipment slot is determined by the bandwidth allocation identification component. The bandwidth resources are automatically identified and allocated on the basis of the bandwidth allocation identification component without occupying any resource of GPIO (General Purpose Input / Output), so that the technical problems that a GPIO identification circuit needs to be designed to make a bandwidth allocation table and the allocation efficiency is low are solved, and the purposes of not occupying GPIO resources, saving GPIO and improving the bandwidth allocation efficiency are achieved. And the distribution efficiency is improved.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

The invention discloses a multi-channel fan control system and device based on a CPLD and a switch, and relates to the technical field of electronic equipment temperature control, the multi-channel fan control system based on the CPLD comprises an automatic system control chip, a CPLD device and a temperature acquisition module; according to the scheme, the CPLD device is introduced to serve as an intermediate control layer, so that the burden of a system control chip is remarkably relieved. And the temperature acquisition module focuses on temperature data acquisition of each fan area, so that the accuracy and the real-time performance of temperature monitoring are ensured. And the system control chip only needs to process the temperature data and generate the driving signal, so that the GPIO (General Purpose Input / Output) usage amount and the logic resource occupation are greatly reduced. The technical problem that a plurality of paths of four-wire fans occupy a large number of GPIO and system logic resources is solved.

The invention discloses a voltage regulation module, electronic equipment and a voltage regulation method. The voltage regulation module provided by the invention comprises a target module, a PMIC module and a voltage detection module, the voltage detection module is located between the target module and the PMIC module; the PMIC module comprises a voltage output port and a GPIO (General Purpose Input / Output) port; a voltage output port of the PMIC module is connected with a target module through a power supply wire; the voltage detection module is provided with a first input end, a second input end and an output end, the first input end of the voltage detection module and the second input end of the voltage detection module are connected with the target module through the power supply wire, and the output end of the voltage detection module is connected with the GPIO port of the PMIC module.

The invention discloses an automatic test-oriented communication protocol and sequential logic cooperative control system, and relates to the technical field of nuclear field instrument and control system test, and the system comprises a 7-slot computer cage, a controller, a function card, a dual-path full duplex communication link, and a power supply monitoring module. The controller is fixed at the slot 0 of the 7-slot cage, and the function card is inserted in the slot 1 to the slot 6 in a mixed manner. And the controller is connected with each function card through a double-path full duplex communication link, is linked with the power supply monitoring module through a GPIO (General Purpose Input / Output) signal so as to monitor and control the power supply of the function card, and is also connected with the HMI through a gigabit Ethernet. The controller receives a test case of the HMI based on a first preset communication protocol, generates a test instruction, packages the test instruction into a control frame through a second preset communication protocol, issues the control frame according to three time sequence regulation and control modes, receives the state and test data returned by the function card, and intervenes the abnormal function card through the power supply monitoring module. And the function card analyzes the instruction, executes a test, collects and returns data, and reports the operation state at the same time.

The invention relates to a GPIO (General Purpose Input / Output) input anti-shake method for a domestic PLC (Programmable Logic Controller), and relates to the technical field of industrial automation. The method comprises the following steps: configuring an anti-shake structural body for each GPIO channel; and for each GPIO channel, if the state flag of the GPIO channel is an uninitialized state, carrying out initialization sampling for a preset number of times according to a preset stable waiting time interval. And setting a state flag and a current sampling value according to an initialized sampling result. And for each GPIO channel, if the state flag of the GPIO channel is a stable state or a filtering starting state, periodically sampling a GPIO input signal based on a timing interruption mechanism and a preset interruption period. And updating a state flag and a current sampling value according to a periodic sampling result on the basis of a stable frequency threshold value of the GPIO channel. And if the state flag of the GPIO channel is a stable state, updating the stable value of the GPIO channel to the current sampling value. According to the invention, the signal stable acquisition capability and the overall reliability of the PLC in an industrial interference environment can be improved.

The invention discloses an on-orbit SSD (Solid State Disk) data ground recovery method, which comprises the following steps that: a HOST end communicates with a JTAG (Joint Test Action Group) interface of an SSD main control CPU (Central Processing Unit) through a GPIO (General Purpose Input / Output) pin and a simulated JTAG time sequence, controls the HOST end to enter a debugging mode and then controls an NIS (Network Interface Server) peripheral to read data from an NAND Flash, transmits the data to the HOST end through the JTAG interface, marks the physical address of the data and then downloads the data to the ground; the ground device forms a manufacturer-defined write instruction according with a front-end interface protocol of the in-orbit SSD according to the data and the physical address, issues the write instruction to the ground SSD, and writes the data into the ground SSD according to the physical address; and performing power-down restarting on the ground SSD to recover data from the on-orbit SSD. In an extreme space environment, under the condition that firmware codes cannot be operated by SSD equipment due to RAM device faults, it can still be guaranteed that the stored data of the SSD can be recovered on the ground.

The embodiment of the utility model provides a GPIO (General Purpose Input / Output) circuit of an edge computer. The GPIO circuit comprises a computing power module; a level shifter; a pin GPIO13 of the computing power module is connected with a pin A1 of the level translator; a pin GPIO13 of the computing power module outputs a GPIO13-first level, and a pin B1 of the level converter outputs a GPIO13-second level; a pin GPIO14 of the computing power module is connected with a pin A2 of the level translator; a pin GPIO14 of the computing power module outputs a GPIO14-first level, and a pin B2 of the level converter outputs a GPIO14-second level. According to the embodiment of the invention, the technical problem of insufficient driving force caused by direct external driving of the GPIO port of the traditional computing power module is solved.

The utility model relates to a rechargeable battery management system, which comprises resistors R1, R2, R3, R10 and R11, a voltage division circuit, capacitors C1, C6 and C8, power supply chips U1 and U2 and an external battery V18650, one end of the resistor R1 is connected with the DDVDD, and the other end of the resistor R1 is connected with a No.6 pin CHGB of the power supply chip U2; one end of the resistor R2 is connected with the GND, and the other end of the resistor R2 is connected with the fourth pin PWM of the power supply chip U2; the voltage division circuit is electrically connected with an external battery V18650, a No.3 output pin OUT of the power supply chip U2, a battery voltage monitoring GPIO (General Purpose Input / Output) port Battery18650ADC of the MCU, a matched battery voltage monitoring GPIO port Battery18650ADC of the MCU and GND (Ground) respectively; the device is reasonable in design, compact in structure and convenient to use.

The utility model discloses an isolation communication circuit for on-site definition of GPIO pin types of a single-chip microcomputer, which belongs to the technical field of electronic circuits and comprises an input / output end IO, a peripheral output end, a peripheral input end, a first optical coupler isolation circuit and a second optical coupler isolation circuit. The input / output end IO is respectively connected with one end of the first optocoupler isolation circuit and one end of the second optocoupler isolation circuit, the other end of the first optocoupler isolation circuit is connected with the peripheral output end, and the other end of the second optocoupler isolation circuit is connected with the peripheral input end. By integrating a peripheral isolation input or output type circuit of the GPIO pin, the field definition of the input or output type of the GPIO pin is realized.

An electronic device is provided. The electronic device includes a battery, a power management module, a charging circuit, and a processor including a central processing unit (CPU) and a plurality of intellectual property (IP) blocks. The charging circuit is connected to the processor and includes a first pin to output a first overcurrent warning signal. The power management module is connected to the processor and includes a second pin to output a reset warning signal. The processor includes a first general purpose input output (GPIO) pin to receive the first overcurrent warning signal, and is configured to reduce at least one clock frequency among a plurality of clock frequencies set to each of the CPU and the plurality of IP blocks, or reduce at least one operation clock frequency of components inside the electronic device when the first overcurrent warning signal is received through the first GPIO pin.

The present invention relates to a device and a system for debugging a solid state disk device, the device comprising: a joint test action group add-on board; and a Raspberry Pi. The Raspberry Pi comprises a general purpose input output interface coupled to the joint test action group add-on board; and a processing unit coupled to the general purpose input output interface. The processing unit is configured to emulate a plurality of joint test action group commands to the solid state disk device through the general purpose input output interface to dump data generated by the solid state disk device during runtime of the solid state disk device. Using the device as described above can reduce the cost required to debug the solid state disk device.

The utility model discloses a dynamically configurable power supply conversion module, which comprises a current monitoring circuit, a DC / DC power supply conversion circuit and an MCU processor, the MCU processor is provided with a plurality of analog / digital conversion interfaces, the input end of the current monitoring circuit is connected with an external power supply, the output end of the current monitoring circuit is connected with the DC / DC power supply conversion circuit and is connected with one analog / digital conversion interface, and the output end of the current monitoring circuit is connected with the DC / DC power supply conversion circuit. The DC / DC conversion circuit is connected with a general purpose input / output (GPIO) port and a serial peripheral interface (SPI) bus interface of the MCU processor, and the MCU processor is connected with an external controller through an inter-integrated circuit (I2C) bus and is respectively connected with a plurality of output ends of the DC / DC conversion circuit through a plurality of other analog / digital conversion interfaces. The power conversion module is convenient to integrate, can be directly connected with an external controller or receive configuration data input by an external user, realizes dynamic configuration of a power supply, and reports the working state monitoring of the power conversion module at the same time.

The invention relates to the technical field of data processing, in particular to a data reporting method and system for slave devices and a storage medium, and the method comprises the steps: generating a clock signal before slave selection signals corresponding to a plurality of slave devices enter a low level; when the falling edge of the slave selection signal identifies that the clock signal is at a low level, controlling the levels of the MISO ports of the plurality of slave devices to be in a high impedance state; wherein the plurality of slave devices are provided with corresponding identification information; the master device sends the candidate identification information to the slave devices through the MOSI port, so that the plurality of slave devices compare the candidate identification information with own identification information; if the candidate identification information is matched with the identification information of the candidate slave device, the candidate slave device is adopted to adjust the MISO port from the high resistance state to the low level based on the candidate identification information, and a notification message representing the data sending requirement is reported. According to the method, the access of one master device to a plurality of slave devices can be realized without adding chip selection and GPIO (General Purpose Input / Output).

The invention provides a self-adaptive external input voltage adjustable GPIO (General Purpose Input / Output) circuit, which comprises a signal transmission module, the input end of the signal transmission module is used for inputting an external input signal, the output end of the signal transmission module is used for being electrically connected with an internal chip, and the signal transmission module comprises a first switching device; the external input signal is a signal input into the input and output circuit by an external circuit; the input end of the voltage control module is used for inputting an external input signal, the output end of the voltage control module is electrically connected with the control end of the first switching device, and the voltage control module is used for driving the first switching device to be switched on under the condition that the voltage of the external input signal is greater than a preset voltage; the voltage of the signal input to the internal chip by the signal transmission module is smaller than or equal to the preset voltage. The circuit can realize self-bias voltage protection when a chip is not powered on, can prevent overvoltage when the chip works normally, can broaden the regulation range of IO threshold voltage, and can meet the actual application requirements.

The utility model discloses a single battery temperature detection device, which comprises an MCU chip and an AFE chip which are in communication connection, and further comprises measuring circuits which are in one-to-one correspondence connection with temperature sensors, and further comprises a plurality of alternative analog switches, every two measuring circuits correspond to one alternative analog switch and one GPIO (General Purpose Input / Output) channel of the AFE chip; two input channels of each alternative analog switch are electrically connected with the output ends of the two corresponding measuring circuits respectively, and the output end of each alternative analog switch is electrically connected with the corresponding GPIO channel respectively; and one digital output port of the MCU chip is connected with the gating control ends of all the alternative analog switches. According to the utility model, double channel expansion can be realized through the plurality of alternative analog switches, 1 / 2 temperature measurement channels can be realized each time, the measurement efficiency is improved, and meanwhile, the device also has the advantages of simple control logic, high GPIO (General Purpose Input / Output) channel utilization rate and the like.