115 results about "General-purpose input/output" patented technology

The invention discloses a server mainboard, a server, a bandwidth acquisition method, a product, equipment and a medium, and relates to the technical field of server interface control, the server mainboard comprises a bandwidth allocation identification component arranged for a bus equipment slot, the bandwidth allocation identification component can identify the bandwidth allocation condition of the corresponding bus equipment slot, and the bandwidth allocation condition of the corresponding bus equipment slot is determined by the bandwidth allocation identification component. The bandwidth resources are automatically identified and allocated on the basis of the bandwidth allocation identification component without occupying any resource of GPIO (General Purpose Input / Output), so that the technical problems that a GPIO identification circuit needs to be designed to make a bandwidth allocation table and the allocation efficiency is low are solved, and the purposes of not occupying GPIO resources, saving GPIO and improving the bandwidth allocation efficiency are achieved. And the distribution efficiency is improved.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

The invention discloses an automatic test-oriented communication protocol and sequential logic cooperative control system, and relates to the technical field of nuclear field instrument and control system test, and the system comprises a 7-slot computer cage, a controller, a function card, a dual-path full duplex communication link, and a power supply monitoring module. The controller is fixed at the slot 0 of the 7-slot cage, and the function card is inserted in the slot 1 to the slot 6 in a mixed manner. And the controller is connected with each function card through a double-path full duplex communication link, is linked with the power supply monitoring module through a GPIO (General Purpose Input / Output) signal so as to monitor and control the power supply of the function card, and is also connected with the HMI through a gigabit Ethernet. The controller receives a test case of the HMI based on a first preset communication protocol, generates a test instruction, packages the test instruction into a control frame through a second preset communication protocol, issues the control frame according to three time sequence regulation and control modes, receives the state and test data returned by the function card, and intervenes the abnormal function card through the power supply monitoring module. And the function card analyzes the instruction, executes a test, collects and returns data, and reports the operation state at the same time.

The invention relates to a GPIO (General Purpose Input / Output) input anti-shake method for a domestic PLC (Programmable Logic Controller), and relates to the technical field of industrial automation. The method comprises the following steps: configuring an anti-shake structural body for each GPIO channel; and for each GPIO channel, if the state flag of the GPIO channel is an uninitialized state, carrying out initialization sampling for a preset number of times according to a preset stable waiting time interval. And setting a state flag and a current sampling value according to an initialized sampling result. And for each GPIO channel, if the state flag of the GPIO channel is a stable state or a filtering starting state, periodically sampling a GPIO input signal based on a timing interruption mechanism and a preset interruption period. And updating a state flag and a current sampling value according to a periodic sampling result on the basis of a stable frequency threshold value of the GPIO channel. And if the state flag of the GPIO channel is a stable state, updating the stable value of the GPIO channel to the current sampling value. According to the invention, the signal stable acquisition capability and the overall reliability of the PLC in an industrial interference environment can be improved.

The invention discloses an on-orbit SSD (Solid State Disk) data ground recovery method, which comprises the following steps that: a HOST end communicates with a JTAG (Joint Test Action Group) interface of an SSD main control CPU (Central Processing Unit) through a GPIO (General Purpose Input / Output) pin and a simulated JTAG time sequence, controls the HOST end to enter a debugging mode and then controls an NIS (Network Interface Server) peripheral to read data from an NAND Flash, transmits the data to the HOST end through the JTAG interface, marks the physical address of the data and then downloads the data to the ground; the ground device forms a manufacturer-defined write instruction according with a front-end interface protocol of the in-orbit SSD according to the data and the physical address, issues the write instruction to the ground SSD, and writes the data into the ground SSD according to the physical address; and performing power-down restarting on the ground SSD to recover data from the on-orbit SSD. In an extreme space environment, under the condition that firmware codes cannot be operated by SSD equipment due to RAM device faults, it can still be guaranteed that the stored data of the SSD can be recovered on the ground.

The embodiment of the utility model provides a GPIO (General Purpose Input / Output) circuit of an edge computer. The GPIO circuit comprises a computing power module; a level shifter; a pin GPIO13 of the computing power module is connected with a pin A1 of the level translator; a pin GPIO13 of the computing power module outputs a GPIO13-first level, and a pin B1 of the level converter outputs a GPIO13-second level; a pin GPIO14 of the computing power module is connected with a pin A2 of the level translator; a pin GPIO14 of the computing power module outputs a GPIO14-first level, and a pin B2 of the level converter outputs a GPIO14-second level. According to the embodiment of the invention, the technical problem of insufficient driving force caused by direct external driving of the GPIO port of the traditional computing power module is solved.

The utility model relates to a rechargeable battery management system, which comprises resistors R1, R2, R3, R10 and R11, a voltage division circuit, capacitors C1, C6 and C8, power supply chips U1 and U2 and an external battery V18650, one end of the resistor R1 is connected with the DDVDD, and the other end of the resistor R1 is connected with a No.6 pin CHGB of the power supply chip U2; one end of the resistor R2 is connected with the GND, and the other end of the resistor R2 is connected with the fourth pin PWM of the power supply chip U2; the voltage division circuit is electrically connected with an external battery V18650, a No.3 output pin OUT of the power supply chip U2, a battery voltage monitoring GPIO (General Purpose Input / Output) port Battery18650ADC of the MCU, a matched battery voltage monitoring GPIO port Battery18650ADC of the MCU and GND (Ground) respectively; the device is reasonable in design, compact in structure and convenient to use.

The utility model discloses an isolation communication circuit for on-site definition of GPIO pin types of a single-chip microcomputer, which belongs to the technical field of electronic circuits and comprises an input / output end IO, a peripheral output end, a peripheral input end, a first optical coupler isolation circuit and a second optical coupler isolation circuit. The input / output end IO is respectively connected with one end of the first optocoupler isolation circuit and one end of the second optocoupler isolation circuit, the other end of the first optocoupler isolation circuit is connected with the peripheral output end, and the other end of the second optocoupler isolation circuit is connected with the peripheral input end. By integrating a peripheral isolation input or output type circuit of the GPIO pin, the field definition of the input or output type of the GPIO pin is realized.

An electronic device is provided. The electronic device includes a battery, a power management module, a charging circuit, and a processor including a central processing unit (CPU) and a plurality of intellectual property (IP) blocks. The charging circuit is connected to the processor and includes a first pin to output a first overcurrent warning signal. The power management module is connected to the processor and includes a second pin to output a reset warning signal. The processor includes a first general purpose input output (GPIO) pin to receive the first overcurrent warning signal, and is configured to reduce at least one clock frequency among a plurality of clock frequencies set to each of the CPU and the plurality of IP blocks, or reduce at least one operation clock frequency of components inside the electronic device when the first overcurrent warning signal is received through the first GPIO pin.

The present invention relates to a device and a system for debugging a solid state disk device, the device comprising: a joint test action group add-on board; and a Raspberry Pi. The Raspberry Pi comprises a general purpose input output interface coupled to the joint test action group add-on board; and a processing unit coupled to the general purpose input output interface. The processing unit is configured to emulate a plurality of joint test action group commands to the solid state disk device through the general purpose input output interface to dump data generated by the solid state disk device during runtime of the solid state disk device. Using the device as described above can reduce the cost required to debug the solid state disk device.

The utility model discloses a dynamically configurable power supply conversion module, which comprises a current monitoring circuit, a DC / DC power supply conversion circuit and an MCU processor, the MCU processor is provided with a plurality of analog / digital conversion interfaces, the input end of the current monitoring circuit is connected with an external power supply, the output end of the current monitoring circuit is connected with the DC / DC power supply conversion circuit and is connected with one analog / digital conversion interface, and the output end of the current monitoring circuit is connected with the DC / DC power supply conversion circuit. The DC / DC conversion circuit is connected with a general purpose input / output (GPIO) port and a serial peripheral interface (SPI) bus interface of the MCU processor, and the MCU processor is connected with an external controller through an inter-integrated circuit (I2C) bus and is respectively connected with a plurality of output ends of the DC / DC conversion circuit through a plurality of other analog / digital conversion interfaces. The power conversion module is convenient to integrate, can be directly connected with an external controller or receive configuration data input by an external user, realizes dynamic configuration of a power supply, and reports the working state monitoring of the power conversion module at the same time.

The invention relates to the technical field of data processing, in particular to a data reporting method and system for slave devices and a storage medium, and the method comprises the steps: generating a clock signal before slave selection signals corresponding to a plurality of slave devices enter a low level; when the falling edge of the slave selection signal identifies that the clock signal is at a low level, controlling the levels of the MISO ports of the plurality of slave devices to be in a high impedance state; wherein the plurality of slave devices are provided with corresponding identification information; the master device sends the candidate identification information to the slave devices through the MOSI port, so that the plurality of slave devices compare the candidate identification information with own identification information; if the candidate identification information is matched with the identification information of the candidate slave device, the candidate slave device is adopted to adjust the MISO port from the high resistance state to the low level based on the candidate identification information, and a notification message representing the data sending requirement is reported. According to the method, the access of one master device to a plurality of slave devices can be realized without adding chip selection and GPIO (General Purpose Input / Output).

The invention provides a self-adaptive external input voltage adjustable GPIO (General Purpose Input / Output) circuit, which comprises a signal transmission module, the input end of the signal transmission module is used for inputting an external input signal, the output end of the signal transmission module is used for being electrically connected with an internal chip, and the signal transmission module comprises a first switching device; the external input signal is a signal input into the input and output circuit by an external circuit; the input end of the voltage control module is used for inputting an external input signal, the output end of the voltage control module is electrically connected with the control end of the first switching device, and the voltage control module is used for driving the first switching device to be switched on under the condition that the voltage of the external input signal is greater than a preset voltage; the voltage of the signal input to the internal chip by the signal transmission module is smaller than or equal to the preset voltage. The circuit can realize self-bias voltage protection when a chip is not powered on, can prevent overvoltage when the chip works normally, can broaden the regulation range of IO threshold voltage, and can meet the actual application requirements.

A system and method for automatically detecting a type of memory card inserted into a portable computing device. The system may include a system on chip capable of detecting a first type of memory card and a second type of memory card. For this detection, the system on chip does not have / does not use an analog switch. The first memory card may be a secure digital express memory card. Meanwhile, the second memory card may be a secure digital memory card. The system on chip may include a general purpose input / output pin. The general purpose input / output pin may activate a first communication bus protocol associated with the secure digital express memory card in response to receiving a first signal. The first signal may be generated by a reserved for future use pin on the first type of memory card.

The utility model discloses a single battery temperature detection device, which comprises an MCU chip and an AFE chip which are in communication connection, and further comprises measuring circuits which are in one-to-one correspondence connection with temperature sensors, and further comprises a plurality of alternative analog switches, every two measuring circuits correspond to one alternative analog switch and one GPIO (General Purpose Input / Output) channel of the AFE chip; two input channels of each alternative analog switch are electrically connected with the output ends of the two corresponding measuring circuits respectively, and the output end of each alternative analog switch is electrically connected with the corresponding GPIO channel respectively; and one digital output port of the MCU chip is connected with the gating control ends of all the alternative analog switches. According to the utility model, double channel expansion can be realized through the plurality of alternative analog switches, 1 / 2 temperature measurement channels can be realized each time, the measurement efficiency is improved, and meanwhile, the device also has the advantages of simple control logic, high GPIO (General Purpose Input / Output) channel utilization rate and the like.

The invention discloses an intelligent decorative lighting control circuit and an intelligent lamp. The intelligent decorative lighting control circuit comprises a main control chip, a storage chip, a power amplifier chip, a key circuit, an infrared receiving circuit, an audio input circuit, an MOS tube driving circuit and a step-down conversion circuit, the main control chip is connected with the storage chip through an SPI (Serial Peripheral Interface), is connected with the input end of the power amplifier chip through a DAC (Digital-to-Analog Converter) output pin, and is respectively connected with the key circuit, the infrared receiving circuit, the audio input circuit and the MOS tube driving circuit through GPIO (General Purpose Input / Output) pins; the input end of the step-down conversion circuit is connected with an external direct-current power supply, and the output end is respectively connected with power supply pins of the main control chip, the storage chip and the power amplifier chip; and the main control chip reads audio data in the storage chip according to an input signal of the key circuit or the infrared receiving circuit and outputs the audio data to the power amplifier chip, or generates a PWM control signal and outputs the PWM control signal to the MOS tube driving circuit so as to perform intelligent cooperative control on the lamp. According to the invention, the system hardware complexity and cost are reduced.

This application provides a communication method, apparatus, medium, and system for a general-purpose input / output port. The method includes: a first device determining first communication information to be sent and querying a first mapping table to determine a first duty cycle corresponding to the first communication information; encoding the first communication information into a first pulse signal according to the first duty cycle; sending the first pulse signal to a second device; and the second device sending a second pulse signal to the first device, wherein the second pulse signal is obtained by the second device encoding the second communication information according to a second duty cycle corresponding to the second communication information to be sent. Embodiments of this application encode information using different duty cycles, thereby achieving differentiation between multiple instructions and multiple states. This application can solve the problems that general-purpose input / output ports cannot differentiate information or encode multiple instructions and multiple states, enabling general-purpose input / output ports to support bidirectional, multi-instruction, and multi-state data interaction.

The utility model discloses a communication board card and an LCU (Local Control Unit) case comprising the communication board card, particularly relates to the technical field of communication equipment, and is technically characterized in that the communication board card comprises a plurality of communication devices, and each communication device comprises a control processor; the first communication equipment, the second communication equipment and the third communication equipment are connected with the control processor; each of the plurality of control processors is provided with a GPIO (General Purpose Input / Output) input port and a GPIO output port, and the plurality of control processors are mutually connected through the GPIO input ports and the GPIO output ports; the plurality of first communication devices are connected with an upper computer, the plurality of second communication devices are connected with a first external communication bus, and the plurality of third communication devices are connected with a second external communication bus.

The invention provides an equipment interconnection and bidirectional control system and method based on a single GPIO (General Purpose Input / Output) line. The system comprises host equipment, external equipment and the single GPIO line, the host equipment and the external equipment are interconnected through a single GPIO (General Purpose Input / Output) line; the GPIO line is used for transmitting a control signal; the control signal is a reset signal or an interrupt signal, and the external device is used for executing a reset operation based on the reset signal; and the host equipment is used for calling a corresponding interrupt processing program based on the interrupt signal. According to the invention, the number of interconnection signal lines between devices is reduced, the internal interface interconnection space of the server is saved, the design and layout of the server are simplified, the integration level and performance of the server are improved, and the cost and maintenance difficulty are reduced; the method has stability and reliability, and can meet the performance and compatibility requirements of a high-density server.

The invention discloses an SGPIO (Serial General Purpose Input / Output) unified coding method, system and device, and the method is characterized in that the method comprises the steps: powering on a server host, and completing the initialization of a CPLD (Complex Programmable Logic Device) and an SATA / SAS controller; a register and a counter are established, and an SGPIO input Data buffer register, an output Data buffer register and a Clock counter of the SGPIO are established in the CPLD; data frame bit length calculation: the CPLD waits for receiving the SGPIO signal, and calculates the bit length of the input data frame after receiving the input SGPIO signal; whether the bit length of a data frame is equal to 12 bits or not is judged, if the length of the data frame is 12 bits, Clock, Load and Data signals of input SGPIO are directly transmitted to an output IO pin in a transparent mode, and the SGPIO signals of an output interface are completely equal to the SGPIO signals input by the CPLD; and if the data frame length is greater than 12 bits, the signal is processed, so that the SGPIO data of the output port is unified into 12-bit data. By unifying the SGPIO data of the output port into 12 bits, the problem that the bit lengths of SGPIO signals of different devices or interfaces are inconsistent is effectively solved, and the compatibility and standardization degree of the system are remarkably improved.

The utility model relates to the technical field of LED control circuits, in particular to an LED display state control circuit. The control circuit comprises a main chip used for generating a control signal; the plurality of GP IO ports are arranged on the main chip and are used for outputting the control signals; and the LED control circuit is electrically connected with the GPIO ports, receives the control signal and adjusts the on-off state of an LED according to the control signal. The LED display state control circuit provided by the utility model is more flexible. By using a mode of combining a plurality of GPIO (General Purpose Input / Output) ports with an NPN (Negative-Positive-Negative) triode, independent control on a plurality of LEDs is realized. Specifically, the main chip outputs control signals through a plurality of GP IO ports, and the signals are transmitted to each LED through an NPN triode, so that the on-off state of each LED can be flexibly controlled. The expansibility of the system is improved, and the information displayed by the LED is richer and more diversified.

Systems and methods described herein correspond to supply harvesting operations. Power management circuitry may receive a supply voltage from other power management circuitry. This supply voltage may be a harvested supply from the other power management circuitry. Moreover, some of the power management circuitry may be operated as controller power management circuitry to supply the supply voltage via one or more rails and some of the power management circuitry may be operated as leaf power management circuitry to harvest the supply voltage from the one or more rails. Leaf power management circuitry may exclude a regulator, enabling that leaf power management circuitry to be entered into a lower power mode than previously enabled when the regulator was included.

The invention provides a multi-FPGA (Field Programmable Gate Array) module updating method based on XDMA (Extensible Direct Memory Access) in a heterogeneous platform, which comprises a main control module as a receiving system task requirement and an FPGA module as a co-processing module, wherein the number of the FPGA modules can be zero or multiple. The method is realized based on a PCIe bus, the main control module is interconnected with the FPGA module through the PCIe bus, state information is acquired through a general purpose input / output (GPIO) signal, and according to different slot positions and function requirements, a single-block or multi-block FPGA program is updated under the condition that other functions of the whole machine are not influenced. The step of updating the FPGA module by the main control module under the task requirement is introduced in detail. The scheme is accurate and effective, the function of the FPGA module can be updated under the condition that the system function is not influenced, and the application function flexibility under the heterogeneous platform is improved.

The invention belongs to the technical field of communication, and relates to a method, a device and equipment for configuring a communication protocol at a slave end and a storage medium, at least two GPIO (General Purpose Input / Output) interfaces of a communication interface of a slave are used as detection ports, and the method for configuring the communication protocol at the slave end comprises the following steps: enabling the slave to enter a power-on state, and setting the communication interface to be in an input mode; reading the levels of all the detection ports; comparing the read levels of all the detection ports with pre-stored level truth value information, wherein the level truth value information comprises the levels of all the detection ports of which the communication interfaces are connected with hosts adopting SPI, UART and I2C communication protocols respectively and which are in an idle state; identifying a communication protocol type currently adopted by the host according to a comparison result; the communication interface is configured to support the identified communication protocol type. According to the technical scheme adopted by the invention, the slave computer can support the SPI, UART and I2C communication protocols without designing a plurality of groups of communication interfaces or carrying out model design on various communication protocols.

The invention relates to a screen display control method and system, a terminal and a storage medium. The screen display control system comprises a main control unit, an MCU chip, a converter and a displayer. A GPIO (General Purpose Input / Output) output pin of the MCU chip is connected with the main control unit and outputs an HDMI (High Definition Multimedia Interface) HPD signal to the main control unit so as to simulate a display HPD signal to the main control unit; a DDC signal line of the display is switched through a converter so as to be connected with an I2C interface of the MCU chip and an HDMI DDC signal port of the main control unit at the same time; the converter is used for switching a DDC signal line of the display to be communicated with the MCU chip or the main control unit; signal ports S3 and S4 of the main control unit are respectively connected to a GPIO (General Purpose Input / Output) pin of the MCU chip, and the MCU chip acquires a power supply state of the main control unit through the GPIO pin; according to the scheme, CEC control can be achieved through hardware design and bottom firmware, a large amount of software development cost and time are saved, and meanwhile automatic control and manual control can be achieved more flexibly.

The utility model provides a general purpose input / output (GPIO) pin compatibility testing device, which comprises a Cat.1 communication module and a plurality of resistors, the Cat.1 communication module is provided with a plurality of groups of input pins and a plurality of groups of output pins, and the plurality of resistors are connected between the input pins and the output pins in the plurality of groups of input pins and the plurality of output pins; according to different connections between the input pin and the output pin, changing the pin state of the input pin or the output pin through an instruction of the Cat.1 module; therefore, different GPIO test schemes can be selected according to different GPIOs, the design and development cost is reduced, the automatic production line changing time is shortened, the construction of a production test environment is facilitated, the compatibility of a test tool is improved, and the cost of a test fixture is saved.

A chip configured to be mounted on a carrier. The chip includes a die having an input / output circuit and a general-purpose input / output port, wherein the general-purpose input / output port is electrically conductively connected to the input / output circuit of the die. The chip further includes a package in which the die is at least partially embedded, and at least one metal surface on a mounting side of the chip, wherein the mounting side faces the carrier during mounting, wherein a size of the at least one metal surface is at least 10% of a size of the mounting side, and wherein the general-purpose input / output port is furthermore electrically conductively connected to the at least one metal surface.

The utility model relates to the technical field of circuits, in particular to a motor self-adjusting control circuit and a stamper machine, and the motor self-adjusting control circuit comprises a single-chip microcomputer, an infrared geminate transistor, a stamper motor driving chip and a two-phase stepping motor. A first UART (Universal Asynchronous Receiver / Transmitter) interface of the singlechip is connected with an infrared geminate transistor, a first GPIO (General Purpose Input / Output) interface of the singlechip is connected with an input end of a seal motor driving chip, an output end of the seal motor driving chip is connected with a two-phase stepping motor, and the two-phase stepping motor is connected with one end of a seal; infrared photoelectric signals are detected through the infrared geminate transistors, pulse signals are output to the seal motor driving chip after the single-chip microcomputer receives the infrared photoelectric signals fed back by the infrared geminate transistors, and the rotation angle of the two-phase stepping motor is controlled through the seal motor driving chip, so that the number of rotation turns of the lead screw in the two-phase stepping motor is adjusted, and the seal is achieved. The purpose of controlling the height of the seal is achieved.

A system and method of transmitting signals are provided. The method includes: acquiring a Virtual Pin Port (VPP) lighting signal and a Serial General Purpose Input / Output (SGPIO) lighting signal by a server motherboard, a hard disk backplane being deployed with a target logic device and a set of hard disk slots; and scheduling and switching the VPP lighting signal and the SGPIO lighting signal in an orderly time-division way by using a preset time-division multiplexing manner, so as to transmit the VPP lighting signal and the SGPIO lighting signal to the target logic device through a same lighting cable.

A method and system are provided herein for serial peripheral interface (SPI) control. The method may first include setting a general purpose input / output (GPIO) register to select an SPI data bus from at least one of an SPI master. The method may proceed to setting the SPI master to send a first data set of SPI serial data. The first data set may be provided to an SPI slave device. A second data set may be retrieved from the SPI slave device.