FPGA (field programmable gate array)-based universal fixed-point-number neural network convolution accelerator hardware structure

Abstract

The invention discloses an FPGA (field programmable gate array)-based universal fixed-point-number neural network convolution accelerator hardware structure which comprises a universal AXI4 high-speed bus interface, a universal GPIO (general purpose input / output) interface, a universal convolver, a universal read-write control unit, a universal state controller and a universal convolution result buffer. Universal memory hardware is provided, and high-parallel read-write operations are supported; the universal convolver can be used for accurate configuration of fixed point numbers, configuration of convolution operation levels and high-parallel convolution operation in coordination with high-parallel read-write operations after data storage; the universal read-write control unit includes ram, rom and Fifo read-write control logics and address generating logics; the universal state controller makes corresponding unit operating reactions aiming at a convolution layer and read-write and calculation processes to control an integral calculation process; the universal convolution result buffer is used for high-speed parallel caching and sending of a processing result to a bus according to a convolution result sectional accumulation method. By verification in application to Yolo algorithm based human face detection and CNN (convolutional neural network) based human face recognition, high operating speed and high data precision are embodied.

Description

technical field [0001] The present invention relates to the technical fields of electronic information and deep learning, and in particular to a general-purpose fixed-point number neural network convolution accelerator hardware structure based on FPGA (Field-Programmable Gate Array, Field Programmable Gate Array). Background technique [0002] Since Hinton and others proposed deep learning in 2006, artificial intelligence solutions based on Convolutional Neural Network (CNN) have become more and more abundant. Some mobile platforms such as drones and robots use convolutional neural networks. Build applications such as speech recognition, face recognition, image recognition, and more. Due to the huge amount of calculation of the convolutional neural network, GPU (Graphic Processing Unit, graphics processing unit), FPGA, ASIC (Application Specific Integrated Circuit, application specific integrated circuit) and other hardware computing support, such as represented by Nvidia, a...

AI Technical Summary

Problems solved by technology

Only FPGA-side logic is used to control the reading and writing of a large amount of data, and a large number of memory accesses will be performed. The reading and writing control logic is extremely complex, and the increase in power consumption is inevitable. At the same time, these logics are not reusable, that is, for each layer in the network , need to design control logic specially, bring many difficulties to FPGA design

The CPU only needs to operate on the memory to process read and write, which brings a significant reduction in design complexity.

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