Multi-level cache processing method of drive program in embedded type operation system

Abstract

The invention discloses a multi-level cache processing method of a drive program in an embedded type operation system. The multi-level cache processing method comprises the steps of: using a peripheral register of a CPU (Central Processing Unit) as a first-level hardware cache; using a DMA (Direct Memory Access) storage space of the CPU as a second-level hardware cache; when the first-level hardware cache is written fully, generating the interruption of the DMA to ensure that data in the first-level hardware cache is written in the second-level hardware cache; using partial RAM (Random Access Memory) space as a first-level software cache, when the second-level hardware cache is written fully, generating the interruption of the CPU to ensure that data in the second-level hardware cache is written in the first-level software cache for waiting processing; and using partial RAM space as a second-level software cache, starting a corresponding data processing task progress to ensure that invalid data in the first-level software cache is removed and valid data is stored in the second-level software cache. According to the multi-level cache processing method of the drive program in the embedded type operation system, the operation efficiency of the embedded system can be effectively increased.

Description

technical field [0001] The invention relates to an embedded operating system, in particular to a multi-level cache processing method for a driver in the embedded operating system. Background technique [0002] In existing real-time data acquisition equipment, limited to hardware resource conditions such as limited CPU, if the embedded operating system does not undergo multi-level cache processing in the driver program, the multi-concurrent task processing of the embedded operating system and real-time complete Data collection may cause the CPU to frequently enter the high-priority data interruption collection program, resulting in data leakage caused by the interruption of the low-priority collection program, and causing the collected data to be replaced by new data before it can be processed in time. Coverage and other disadvantages greatly affect the operating efficiency. Contents of the invention [0003] The purpose of the present invention is to provide a multi-level...

AI Technical Summary

Problems solved by technology

[0002] In existing real-time data acquisition equipment, limited to hardware resource conditions such as limited CPU, if the embedded operating system does not undergo multi-level cache processing in the driver program, the multi-concurrent task processing of the embedded operating system and real-time complete Data collection may cause the CPU to frequently enter the high-priority data interruption collection program, resulting in data leakage caused by the interruption of the low-priority collection program, and causing the collected data to be replaced by new data before it can be processed in time. Disadvantages such as coverage greatly affect the operating efficiency

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