Manufacturing method of separated grid type flash memory with peripheral circuit

Abstract

The invention relates to a manufacturing method of a separated grid type flash memory with a peripheral circuit. The manufacturing method comprises that a semiconductor base provided with a first area and a second area is provided; grid lamination is formed in the first area; a first polycrystalline silicon layer is precipitated, wherein the thickness of the first polycrystalline silicon layer is the needed thickness of a transistor grid of the peripheral circuit; a silicon dioxide layer is formed in the second area; the second silicon dioxide layer is precipitated, at least the surface of the first polycrystalline silicon layer and a concave pit in junction of the first polycrystalline silicon layer and the silicon dioxide layer are filled; the whole is grinded to be smooth in surface in a chemical and mechanical mode; whole etching is conducted until a hard mask film layer is exposed from the first area; and the silicon dioxide layer is removed. According to the manufacturing method of the separated grid type flash memory with the peripheral circuit, the problems that performance of terminal insulation is bad due to chemical and mechanical grinding and residual of polycrystalline silicon caused by local high and low range in a peripheral area are avoided due to organic combination of advantages of chemical and mechanical grinding and terminal detecting of etching, and the circumstance that dielectric layers on lower layer especially a substrate silicon layer are damaged due to over etching of the bottom of the surface concave pit in the process of direct etching is avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a split gate type flash memory with peripheral circuits. Background technique [0002] Random access memory, such as DRAM and SRAM, has the problem of data loss after power failure during use. To overcome this problem, various embedded split-gate flash memories have been designed and developed. At present, the flash memory based on the floating gate concept has become the most common embedded split-gate flash memory due to its small cell size and good working performance. [0003] The gate structure of one of the split-gate flash memory transistors is as follows figure 1 , including a gate stack structure of separated gates, an erasable gate 1 between two adjacent gate stack structures, and word line gates 2 respectively located on two sides of the two gate stack structures away from each other. Wherein, the gate stack structure in...

AI Technical Summary

Problems solved by technology

Due to the local unevenness caused by shallow trench isolation on the substrate, it will cause the uneven surface of the silicon oxide layer caused by the local height difference, which has always caused the problem of polysilicon residue in the pits on the surface of the silicon oxide layer.

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