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Low-latency SIMD architecture for multiple iterative decoders arranged in parallel

A decoder and iterative technology, applied in the field of decoders, can solve problems such as aggravated delay, additional chip space, and shortcomings.

Active Publication Date: 2017-10-27
MARVELL ASIA PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Systems of less complexity using controllers experience exacerbated delays when processing data from channels with different characteristics
On the other hand, although using a separate controller for each channel can alleviate this problem, it consumes more power and requires additional chip space for the additional controller
Thus, both single-controller and multi-controller approaches to iterative decoders suffer from the disadvantage of

Method used

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  • Low-latency SIMD architecture for multiple iterative decoders arranged in parallel
  • Low-latency SIMD architecture for multiple iterative decoders arranged in parallel
  • Low-latency SIMD architecture for multiple iterative decoders arranged in parallel

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Embodiment Construction

[0018] Example methods, apparatus, and other embodiments associated with low-latency architectures for high-throughput iterative decoders are described herein. In one embodiment, the architecture includes a Single Instruction Multiple Data (SIMD) architecture. Processing latency for iterative decoders is reduced by controlling the decoders to independently start decoding sequences at the granularity of iterations rather than waiting for multiple decoders to start together. By introducing the ability for a decoder to start a new decoding sequence at an iteration while other decoders are within the decoding sequence, the maximum latency is reduced to one iteration.

[0019] Thus, iterative decoders, such as error correction decoders (eg, Low Density Parity Check (LDPC) decoders, Soft Output Viterbi Algorithm (SOVA) decoders), can be implemented in a low-latency architecture with a single controller. A single controller operates with a finer granularity. In this way, architectu...

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Abstract

An apparatus (100) comprising: a set of buffers (130) for receiving input from respective channels, a set of iterative channel decoders (120) configured for receiving data from their respective buffers, and a controller (110 ), configured to control each decoder individually to initiate a decoding sequence based on the occurrence of a global transition point that occurs periodically for the set of decoders in synchronization with iterations in the decoder.

Description

[0001] Cross References to Related Applications [0002] This patent disclosure claims the benefit of US Provisional Application No. 61 / 430,653, filed January 7, 2011, which is hereby incorporated by reference in its entirety. technical field [0003] Embodiments of the present invention relate generally to decoders and, in particular, to low-latency SIMD architectures for multiple iterative decoders arranged in parallel. Background technique [0004] The background description provided herein is for the purpose of generally presenting the context of the disclosure. The work of the presently named inventors is neither expressly nor implicitly admitted to the extent that this work is described in this Background section, and aspects of that description may not otherwise be qualified as prior art at the time of filing. prior art in this disclosure. [0005] Many forms of electronic communication use iterative functions when manipulating data. For example, when a communicat...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/29H03M13/37
CPCH03M13/2957H03M13/6561H03M13/6569
Inventor N·库马尔姚恩龄
Owner MARVELL ASIA PTE LTD