Memory test method

Abstract

The invention relates to a memory test method, which includes: 1) writing data; 2) reading data; 3) if the address line digit of a to-be-tested memory is lower than or equal to the address line digit of an address generator ATE, making use of the address generator ATE to see whether the read data and written data are the same so as to judge whether all memory cells of the to-be-tested memory work normally; if the address line digit of the to-be-tested memory is higher than the address line digit of the address generator ATE, dividing the address line digit of the to-be-tested memory into low digit address lines and high digit address lines; according to the increase of fixed addresses, partitioning all the memory cells of the tested memory into blocks, increasing the fixed addresses from all 0 to all 1, and dividing a memory cell along with every 1 increase; and connecting the low digit address lines to the address generator ATE, which can automatically generate address data. The method provided in the invention has the advantages of effective use of ATE resources, reduction of test pattern compilation time and improvement of programming efficiency.

Description

technical field [0001] The invention belongs to the field of computer testing, and relates to a testing method, in particular to a memory testing method. Background technique [0002] With the rapid development of microelectronics technology and the trend of miniaturization and integration of electronic equipment, the production and application of large-capacity memories are more extensive, which brings higher requirements for the testing of this type of devices. ATE for memory testing uses address generators to automatically generate address data, and the size of memory suitable for testing is limited by address generators. At present, for devices with a larger capacity than the number of addresses in the address generator, if the full address is to be traversed, the method of handwriting address graphics is often used. The workload of programmers is heavy, and the depth of pin graphics is limited (mostly between 128K and 16M) ), to complete the writing of the whole block ...

AI Technical Summary

Problems solved by technology

ATE for memory testing uses address generators to automatically generate address data, and the size of memory suitable for testing is limited by address generators

At present, for devices with a larger capacity than the number of addresses in the address generator, if the full address is to be traversed, the method of handwriting address graphics is often used. The workload of programmers is heavy, and the depth of pin graphics is limited (mostly between 128K and 16M) ), to complete the writing of the whole block, it needs to be divided into multiple graphics