A serial interface flash memory and clock frequency multiplication circuit
A technology of serial interface and clock frequency multiplication, which is applied in the field of circuits, can solve problems such as mutual incompatibility, achieve stable access time, ensure reliable operation, and improve the effect of impact
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Embodiment 1
[0054] Embodiment 1. A serial interface flash memory, such as Figure 4 shown, including:
[0055] The selection circuit is used to select one of the clock signals and the multiplied clock as the clock signal of the serial interface flash memory;
[0056] Clock frequency multiplication circuit, including:
[0057] The first delay module includes a main delay unit and a plurality of first auxiliary delay units connected in series in sequence; wherein the main delay unit receives a clock signal;
[0058] The control module is used to detect the double-delay signal of the output signal of the main delay unit and each first auxiliary delay unit in the first delay module at the falling edge of each clock signal, and according to these double-delay signals The number of middle and high levels correspondingly selects the output signal of the main delay unit in the first delay module or a first auxiliary delay unit as the delay result signal; the main delay unit or the first auxilia...
Embodiment 2
[0091] Embodiment 2. A clock multiplier circuit, which can be used but not limited to provide a clock signal for SPIFLASH in SDR / DDR mode, including:
[0092] The first delay module includes a main delay unit and a plurality of first auxiliary delay units connected in series in sequence; wherein the main delay unit receives a clock signal;
[0093] The control module is used to detect the number of high levels in the double-delayed signals output by the main delay unit and each first auxiliary delay unit in the first delay module at the falling edge of each clock signal, According to the number of the high level, the output signal of the main delay unit or a first auxiliary delay unit in the first delay module is selected as the delay result signal; the main delay unit or the first auxiliary delay The double-delayed signal of the output signal of the unit refers to a signal whose delay time relative to the clock signal is twice the output signal;
[0094] The XOR modu...
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