Array substrate and manufacturing method thereof and display device
A technology of an array substrate and a manufacturing method, applied in the field of liquid crystal displays, can solve the problems of large overlapping area of pixel electrodes and common electrodes, increased equipment difficulty and cost, large storage capacitor Cst, etc. Effect
Inactive Publication Date: 2013-09-18
BOE TECH GRP CO LTD
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AI Technical Summary
Problems solved by technology
[0003] In the existing ADS type display device, due to the large overlapping area and small spacing between the pixel electrode and the common electrode, the storage capacitor Cst is very large, so there are many restrictions on design.
At present, in order to solve the problem of too large Cst, pixel electrodes and common electrodes are usually arranged in a staggered manner, but in general, since the pixel electrodes and common electrodes are made of transparent electrode materials, the staggered arrangement requires precise exposure process This will undoubtedly increase the difficulty and cost of equipment and process control
Method used
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[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention.
[0049] An embodiment of the present invention provides an array substrate, the array substrate includes a gate line, a data line, and a pixel area defined by intersections of the gate line and the data line, the pixel area includes a thin film transistor, and the thin film transistor includes Gate, gate insulating layer, active layer, source and drain. Such as figure 1 As shown, the pixel area includes: a base substrate 11, on which a protrusion 110 is disposed; a first electrode layer 12, and the first electrode layer 12 includes at least one electrically connected first electrode strip 120, the first electrode strip 120 is arranged in the gap of the protrusion 110...
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The embodiment of the invention provides an array substrate and a manufacturing method thereof and a display device, relates to the field of liquid crystal display, and can achieve zero overlapping between public electrodes and pixel electrodes so as to improve the display quality of the display device. The array substrate comprises a grid line, a data line and a pixel region defined by the grid line and the data line in a cross manner, wherein the pixel region comprises a thin film transistor; the thin film transistor comprises a grid electrode, a grid insulation layer, an active layer, a source electrode and a drain electrode; and the pixel region also comprises a substrate, prominences arranged on the substrate at intervals, a first electrode layer comprising at least one electrically connected first electrode strip arranged in gaps between every two prominences, and a second electrode layer comprising at least one electrically connected second electrode strip arranged above the prominences.
Description
technical field [0001] The invention relates to the field of liquid crystal displays, in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] Common liquid crystal display devices in the prior art mainly include AD-SDS (Advanced-Super Dimensional Switching, referred to as ADS, advanced super-dimensional field switch) type, IPS (In Plane Switch, transverse electric field effect) type and TN (Twist Nematic, twisted nematic) type. Among them, the ADS type display device forms a multi-dimensional electric field through the parallel electric field generated by the edge of the pixel electrode in the same plane and the vertical electric field generated between the pixel electrode layer and the common electrode layer, so that all the alignment liquid crystal molecules between the pixel electrodes and directly above the electrodes in the liquid crystal cell Both can generate rotation transformations. [0003] In the e...
Claims
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Patent Timeline
Login to View More IPC IPC(8): G02F1/1343G02F1/1333
CPCG02F1/133345G02F1/134309G02F2201/124G02F1/134363H01L27/1259H01L27/124G02F1/134381G02F1/134372H01L27/1248H01L21/31127H01L21/32133H10K59/12H01L27/1218
Inventor 崔承镇金熙哲宋泳锡刘聖烈
Owner BOE TECH GRP CO LTD