ldmos transistor and its manufacturing method

Abstract

The invention provides an LDMOS transistor and a manufacturing method thereof. The LDMOS transistor is enabled to have a structure similar to that of a JFET (junction field effect transistor) through forming a drain electrode tuning region which is inverted with a source and a drain in a drain drift region. The drain tuning region enables the drift region of the LDMOS transistor to become narrow, thereby improving breakdown voltage, and being conducive to manufacturing device chips with higher breakdown voltage and smaller area. The manufacturing method of the LDMOS transistor does not need an additional mask, is capable of forming the drain tuning region while forming a source region and a drain region by heavy doping, and can be completely compatible with the existing CMOS manufacturing process. Meanwhile, the LDMOS transistor can be enabled to have tenability by extracting a control electrode from the drain tuning region.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an LDMOS transistor and a manufacturing method thereof. Background technique [0002] LDMOS transistor structures are widely used as semiconductor devices for many types of transistor applications such as high voltage MOS field effect transistors. [0003] like figure 1 As shown, a typical LDMOS transistor in the prior art includes: a semiconductor substrate 100 with a P-type well region, an STI (Shallow Trench Isolation Structure) 101 for isolating devices, an N+ doped The source region 102b, the drain region, and the gate structure (Gate) 103 covering the channel region and affecting electron distribution in the channel region. The drain region generally includes a drain contact region 102a and a drain drift region (N-drift region) 104 extending toward the channel region (or gate). Generally, the source S of an LDMOS transistor is drawn from the source region 102 b...

AI Technical Summary

Problems solved by technology

For LDMOS, it has become more and more difficult to increase the breakdown voltage of LDMOS as much as possible while reducing the device area.

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