Conductive structure and method of forming same

Abstract

The present invention relates to a conductive structure for a semiconductor chip and its forming method. The semiconductor chip includes a plurality of first pads and a plurality of second pads, each first pad and each second pad are formed on the semiconductor On a pad area of ​​the substrate, the first area of ​​the pad area is located between a second area and a third area, and the first pads and the second pads intersect each other in the first area. The conductive structure includes a plurality of conductive bumps, which are respectively formed on each first pad and each second pad, so that each conductive bump is electrically connected to the first pad and the second pad; wherein, the conductive bump There is a first bump width in the first region and a second bump width in one of the second region and the third region, and the first bump width is smaller than the second bump width.

Description

technical field [0001] The present invention relates to a conductive structure and its forming method, in particular to a conductive structure for a semiconductor chip and its forming method. Background technique [0002] Flip-chip (Flip-Chip) packaging technology is one of the commonly used semiconductor packaging technologies, which is mainly after the front side of the chip (Chip) is inverted (Filp), and the chip bump (Bump) and the substrate pad (Pad) ) after bonding, the bump is used as a path for electrical conduction between the chip and the substrate. Because the bumps can be evenly distributed on the entire chip with a fine pitch, it can effectively reduce the package volume and increase the circuit density. Therefore, flip-chip packaging technology has been widely used in microprocessor packages, graphics chips and computer chips. technically. [0003] Figure 1A to Figure 1C It is a schematic top view of a conventional semiconductor structure 1 and its formation...

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Problems solved by technology

[0008] An object of the present invention is to provide a conductive structure for a semiconductor chip to solve the problem of uneven etching of the existing under-bump metal layer by the etching solution, and jointly overcome the deformation of the bump caused by the etching solution

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