514 results about "Ion beam etching" patented technology

A method or forming a wrapped-around shielded perpendicular magnetic recording writer pole is disclosed. A structure comprising a leading shield layer and an intermediate layer disposed over the leading shield layer is provided, the intermediate layer comprising a pole material and a dielectric material. A trench is formed in the dielectric material. A non-magnetic layer in the trench is removed via an ion beam etching process. A seed layer is deposited in the trench and over the pole material. A magnetic material comprising a side shield layer is deposited on at least a portion of the seed layer.

A method for manufacturing MTJ pillars for a MTJ memory device. The method includes depositing multiple MTJ layers on a substrate, depositing a hard mask on the substrate and coating a photoresist on the hard mask. Further, alternating steps of reactive ion etching and ion beam etching are performed to isolate MTJ pillars and expose side surfaces of the MTJ layers. An insulating layer is the applied to protect the side surfaces of the MTJ layers. A second insulating layer is deposited before the device is planarized using chemical mechanical polishing.

Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.

Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening. Furthermore, the method includes performing a first angled etching process to at least partially remove the first layer of first fill material from above the semiconductor device by at least partially removing a first portion of the first layer proximate an inlet of the opening without removing a second portion of the first layer proximate the bottom of said opening, and forming a second layer of second fill material above the semiconductor device by forming the second layer inside the opening and above the first layer.

The invention relates to a resistive random access memory based on bismuth iron thin film system and manufacturing method thereof. The memory comprises an insulating substrate (101) layer as the first layer, a lower electrode (102) as the second layer, a bismuth iron thin film (103) as the third layer, an upper electrode (104) as the fourth layer; the manufacturing method utilizes the method thermal evaporation or magnetron sputtering to grow the lower electrode on the insulating substrate layer, utilizes the method of magnetron sputtering, pulsed laser deposition or colloidal sol-gel to grow the bismuth iron thin film on the lower electrode, finally utilizes the method of thermal evaporation or magnetron sputtering to grow the upper electrode on the bismuth iron thin film, and utilizes the method of ultraviolet lithography, electron beam or ion beam etching to obtain the electrode pattern. The memory provided by the invention has excellent electroluminescent resistance effect and good stability, and has simple manufacturing method, low cost and is easy for manufacturing in large scale and commercial process.

The invention discloses a metal etching device and method which can be used in a large-scale integrated circuit industrial manufacturing environment. Particularly, by means of the metal etching device and method, in a vacuum uninterrupted environment, magnetic tunnel junctions of a magnetic random access memory (MRAM) are subjected to etching and etching post-processing in a reactive-ion plasma etching chamber and an ion beam etching chamber and then subjected to coating surface protection in a coating chamber, so that the side wall of the magnetic tunnel junctions are free of metal contamination after being etched, the chemical and physical structures of the magnetic tunnel junctions are consistent with the chemical and physical structures before etching, the magnetic tunnel junctions can be taken out from etching equipment and not destroyed by the air environment, and the yield of MRAM devices is effectively increased. In addition, the metal etching device and method are also applicable to etching of resistive random access memories and other metals.

A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.

Methods are disclosed generally directed to design and synthesis of quantum dot nanoparticles having improved uniformity and size. In a preferred embodiment, a release layer is deposited on a semiconductor wafer. A heterostructure is grown on the release layer using epitaxial deposition techniques. The heterostructure has at least one layer of quantum dot material, and optionally, one or more layers of reflective Bragg reflectors. A mask is deposited over a top layer and reactive ion-beam etching applied to define a plurality of heterostructures. The release layer can be dissolved releasing the heterostructures from the wafer. Some exemplary applications of these methods include formation of fluorophore materials and high efficiency photon emitters, such as quantum dot VCSEL devices. Other applications include fabrication of other optoelectronic devices, such as photodetectors.

Apparatus and methods for improving the control of the temperature of a supported member, such as a substrate, in high vacuum processing systems, such as ion beam etch (IBE) systems. The apparatus includes thermoelectric devices that transfer heat from a support member supporting the supported member to a liquid-cooled heat exchange member to regulate the temperature of the support member. The method includes cooling the support member with thermoelectric devices that transfer the heat to the liquid-cooled heat exchange member.

A three step ion beam etch (IBE) sequence involving low energy (<300 eV) is disclosed for trimming a sensor critical dimension (free layer width=FLW) to less than 50 nm. A first IBE step has a steep incident angle with respect to the sensor sidewall and accounts for 60% to 90% of the FLW reduction. The second IBE step has a shallow incident angle and a sweeping motion to remove residue from the first IBE step and further trim the sidewall. The third IBE step has a steep incident angle to remove damaged sidewall portions from the second step and accounts for 10% to 40% of the FLW reduction. As a result, FLW approaching 30 nm is realized while maintaining high MR ratio of over 60% and low RA of 1.2 ohm-μm². Sidewall angle is manipulated by changing one or more ion beam incident angles.

A method and system for performing gas cluster ion beam (GCIB) etch processing of various materials are described. In particular, the GCIB etch processing includes setting one or more GCIB properties of a GCIB process condition for the GCIB to achieve one or more target etch process metrics. Furthermore, the GCIB is formed from a pressurized gas mixture containing at least one etch compound and at least one additional gas, wherein the concentration of the at least one etch compound in the GCIB exceeds 5 at % of the pressurized gas mixture.

An integrated micro chip, method of integrating a micro chip, and micro chip integration system are described. In an embodiment, a micro chip such as a micro RFID chip or integrated passive device (IPD) is electrostatically transferred and bonded to a conductive pattern including a line break. In an embodiment, the line break is formed by a suitable cutting technique such as laser laser ablation, ion beam etching, or photolithography with chemical etching to accommodate the micro chip.

An ion beam etching apparatus includes: a processing chamber connected to the plasma generation chamber including an internal space; a plasma generating unit configured to generate plasma in the internal space; an extracting unit configured to extract ions from the plasma, from the internal space to the processing chamber, the extracting unit including first, second and a third electrodes, each of which has a plurality of ion passage holes; a first ring member provided closer to the plasma generation chamber; a second ring member provided closer to the processing chamber; a fixing member having one end and another end, the fixing member penetrating the first, second and third electrodes, and having the one end connected to the first ring member and the other end connected to the second ring member; and a heating unit configured to heat the third electrode from outside of the plasma generation chamber.

The invention provides a holographic blazed grating manufacturing method. Through making a homogeneous grating on a substrate, taking the homogeneous grating as mask, and carrying out oblique ion beam etching, a needed blazed grating is obtained. Since time of positive ion beam etching can be controlled when making the homogeneous grating, a groove depth of the homogeneous grating is accurately controlled. In addition, after obtaining a photoresist raster through interferometric lithography, ashing technology can be increased further, a duty cycle of the photoresist raster is controlled, and a duty cycle of a needed homogeneous grating is controlled. According to the manufacturing method of the present invention, multi-parameter control of blazed grating manufacture is realized, and manufacture precision is raised.

A perpendicular magnetic recording (PMR) head is fabricated with a main pole shielded laterally by a pair of side shields, shielded above by a trailing shield and shielded optionally below by a leading shield. The shields and the seed layers on which they are formed are formed of materials having substantially the same physical characteristics including the same material composition, the same hardness, the same response to processes such as ion beam etching (IBE), chemical mechanical polishing (CMP), mechanical lapping, such as the slider ABS lapping, the same coefficient of thermal expansion (CTE) as well as the same B_s. Optionally, the trailing shield may be formed on a high B_s seed layer to provide the write head with improved down-track performance.

The invention discloses a manufacturing method for a holographic dual-blazed grating. The two blaze angles of the holographic dual-blazed grating are respectively a blaze angle A and a blaze angle B. Different control of the two blaze angles is realized by performing oblique ion beam etching by using a photoresist grating and a homogenous grating as masks on two grating areas A and B, so that a secondary photoresist photoetching process is avoided. When the homogenous grating is manufactured, the positive ion beam etching time can be controlled so that the groove depth of the homogenous grating is controlled precisely. In addition, the homogenous grating mask and the substrate are made of the same material, and the etching rate of the homogenous grating mask and the etching rate of the substrate are kept consistent all the time, so that precise control of the blaze angles can be realized.

The invention provides a magnetic random access memory preparing method. The method comprises the steps that (1) a bottom electrode film layer, a magnetic tunnel junction multilayer film and a hard mask film layer are sequentially formed on a CMOS substrate; (2) patterning defining is carried out on a magnetic tunnel junction pattern, and the hard mask film layer and the magnetic tunnel junction multilayer film are etched and stopped on the bottom electrode film layer; (3) ion beam etching is carried out to remove the capping layer/damaging layer of a sidewall; (4) self-alignment etching is carried out on the bottom electrode film layer until an interlayer dielectric under the bottom electrode film layer is partially etched away; and (5) the dielectric is filled and ground. According to the magnetic random access memory preparing method provided by the invention, a magnetic tunnel junction is firstly prepared, and then a bottom electrode is fabricated to improve the precision of mutualalignment of the bottom electrode and the magnetic tunnel junction; and when the bottom electrode is etched, self-alignment is used without an additional bottom electrode photomask, which reduces theprocess complexity and manufacturing cost and facilitates MRAM mass production.

Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.