A Digital-to-Analog Converter with Segmented Capacitor Array Structure

Abstract

The invention discloses a segmented capacitor array structure digital-to-analog converter, which includes at least two capacitor sub-arrays and at least one bridging capacitor C B , each bridge capacitor C B Capacitor subarrays connecting two weighted adjacent quantization bits, each bridged with a capacitor C B The low-level capacitor sub-array is connected in parallel with an adjustable compensation capacitor C C , compensation capacitor C C The capacitance of the equivalent capacitance of the compensated low-level capacitance sub-array and the bridge capacitance C B The capacitance values ​​of the lowest capacitors in the connected high capacitor sub-arrays are equal. Using the embodiment of the present invention, by introducing a compensation capacitor C with adjustable capacitance C , according to the bridge capacitance C B The parasitic capacitance at the common node of the capacitance sub-arrays at both ends sets the compensation capacitance C C Capacitance, thereby eliminating the capacitance mismatch between the capacitor sub-arrays, further improving its linearity while eliminating gain errors, and ultimately improving the DNL and INL of the successive approximation ADC.

Description

technical field [0001] The invention belongs to the field of electronic circuits, in particular to a digital-to-analog converter with segmented capacitor array structure. Background technique [0002] The successive approximation ADC (Analog to Digital Converter, analog-to-digital converter) based on the principle of charge redistribution has the advantage of lower power consumption, but the number of capacitors significantly increased by the number of digits with binary weights, and the resulting large The problem of input capacitive load makes its application somewhat limited. [0003] In order to solve this problem, the approach in related technologies is to segment the entire capacitor array and connect it with one (two segments) or multiple (multi-segments) bridging capacitors. Such as figure 1 Shown is an 8-bit charge redistribution DAC (Digital to Analog Converter), capacitor C B For bridging capacitors, connect the left and right capacitor sub-arrays respectively....

AI Technical Summary

Problems solved by technology

In order to ensure that the equivalent capacitance of the sub-array on the left side of the bridge capacitor is equal to the lowest capacitance value in the right sub-array during the capacitor redistribution process, the bridge capacitor C B It can only be a non-integer multiple of the unit capacitance C. Obviously, this will introduce a serious mismatch problem and may cause gain errors

[0004] In addition, there is a more serious problem in the above structure, due to the bridge capacitance C B Special binary capacitance design of the left sub-array, node V Q and node V Q and V P There is a non-negligible parasitic capacitance between them, and its size is sensitive to the process implementation (metal routing path, selected level), which will be in C B A large mismatch is introduced between the left and right capacitor sub-arrays, and eventually causes the deterioration of DNL (Differential Nonlinearity, differential nonlinearity) and INL (Integral nonlinearity, integral nonlinearity)

Images