Debug system and method

Abstract

The invention relates to a debug system and method. The debug system comprises a core cluster, a data pool, a data collecting module, a data transmission module, a clock management module and a debug processing module. The core cluster comprises at least one IP core, and the IP cores comprise at least one integrated component. The clock management module is used for generating clock signals to drive the integrated components in the IP cores and the data collecting module to work. The data collecting module is used for collecting data of the integrated components in the IP cores to obtain sampling data and transmitting the sampling data to the debug processing module through the data transmission module. The debug processing module is used for processing the received sampling data and generating corresponding debug data to be transmitted to the data pool through the data transmission module. The data pool processes the debug data and loading the processed data to the input of the corresponding integrated components. The debug system and method can improve debug efficiency and accuracy.

Description

technical field [0001] The invention relates to the field of chip testing, in particular to a debugging system and method. Background technique [0002] With the gradual failure of Moore's Law and the feature size of integrated circuits approaching the physical limit, the power consumption and application diversity, and the product launch cycle are further shortened in response to market needs, which has prompted SOC (System on Chip, system on a chip) to become the current mainstream. integrated circuit design methodology. When trying to integrate massive computing power and control flexibility, but also adapt to some special algorithms (because the delay is too tight or the throughput is too large, or both), the DSP cooperates with the CPU to Some special hardware accelerators on the Internet, as well as SOC systems composed of various interconnection structures and peripheral IPs, have become the mainstream design and implementation methods of SOC systems. However, how t...

AI Technical Summary

Problems solved by technology

However, how to track and debug an SOC chip integrated with multiple DSPs, CPUs and multiple hardware accelerators is a very difficult problem

Due to the large number of control signals to be observed and the large amount of data signals, it is difficult for the general commissioning system to meet the requirements of speed and throughput, and there is no way to tailor it. In the prior art, the CPU, DSP and hardware accelerator are separately debugging, very inefficient and imprecise

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