A debugging system and method

Abstract

The present invention relates to a commissioning system and method. The commissioning system comprises: a core cluster, a data pool, a data acquisition module, a data transmission module, a clock management module, and a commissioning processing module. The core cluster comprises at least one IP core, the IP core comprising at least one integrated component; the clock management module is configured to generate a clock signal to drive the integrated component in the IP core and the data acquisition module to work; the data acquisition module is configured to acquire data of the integrated component in the IP core and obtain sampling data, and transmit the sampling data to the commissioning processing module by using the data transmission module; the commissioning processing module is configured to process the received sampling data, generate corresponding commissioning data and transmit the commissioning data to the data pool by using the data transmission module; and the data pool processes the commissioning data and loads the processed data to the corresponding integrated component for input. The present invention can improve the commissioning efficiency and accuracy.

Description

technical field [0001] The invention relates to the field of chip testing, in particular to a debugging system and method. Background technique [0002] With the gradual failure of Moore's Law and the feature size of integrated circuits approaching the physical limit, the power consumption and application diversity, and the product launch cycle are further shortened in response to market needs, which has prompted SOC (System on Chip, System on Chip) to become the current mainstream integration Circuit Design Methodology. When trying to integrate massive computing power and control flexibility, but also adapt to some special algorithms (because the delay is too tight or the throughput is too large, or both), the DSP cooperates with the CPU to Some special hardware accelerators on the Internet, as well as SOC systems composed of various interconnection structures and peripheral IPs, have become the mainstream design and implementation methods of SOC systems. However, how to ...

AI Technical Summary

Problems solved by technology

However, how to track and debug an SOC chip integrated with multiple DSPs, CPUs and multiple hardware accelerators is a very difficult problem

Due to the large number of control signals to be observed and the large amount of data signals, it is difficult for the general commissioning system to meet the requirements of speed and throughput, and there is no way to tailor it. In the prior art, the CPU, DSP and hardware accelerator are separately debugging, very inefficient and imprecise

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