Circuit for reducing load power consumption when power is switched off
A technology of power shutdown and power consumption, which is applied in the direction of electronic switches, electrical components, pulse technology, etc., can solve the problems of unstable operation of electronic components, shortened life of electronic components, and large power consumption of circuits, so as to reduce the impact , reduce the current, reduce the effect of load power consumption
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[0010] Below in conjunction with accompanying drawing, the present invention is described in detail.
[0011] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.
[0012] like figure 1 Shown is a schematic circuit diagram of a circuit for reducing load power consumption when the power supply is turned off in the present invention.
[0013] A circuit for reducing load power consumption when the power supply is turned off according to the present invention, the circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1, a second NMOS transistor N2, a A resistor R1 and a second resistor R2....
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