Circuit for reducing load power consumption when power is switched off

A technology of power shutdown and power consumption, which is applied in the direction of electronic switches, electrical components, pulse technology, etc., can solve the problems of unstable operation of electronic components, shortened life of electronic components, and large power consumption of circuits, so as to reduce the impact , reduce the current, reduce the effect of load power consumption

Inactive Publication Date: 2014-03-26
ZHENGZHOU DANDIAN TECH SOFTWARE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In smart electronic devices such as PCs, portable computers, tablet computers, and smart phones, when the power is turned off, the circuit needs to do a lot of storage and preparation work. At this time, the power consumption of the circuit is generally large. It will increase accordingly, so it will cause certain instability to some electronic components and shorten the life of these electronic components.

Method used

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  • Circuit for reducing load power consumption when power is switched off

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Embodiment Construction

[0010] Below in conjunction with accompanying drawing, the present invention is described in detail.

[0011] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0012] like figure 1 Shown is a schematic circuit diagram of a circuit for reducing load power consumption when the power supply is turned off in the present invention.

[0013] A circuit for reducing load power consumption when the power supply is turned off according to the present invention, the circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1, a second NMOS transistor N2, a A resistor R1 and a second resistor R2....

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Abstract

This invention discloses a circuit for reducing load power consumption when power is switched off. A voltage source of the circuit is connected to a source electrode of a first PMOS transistor and a source electrode of a second PMOS, and is connected to the grid electrode of the first PMOS transistor and the drain electrode of a second NMOS transistor; the drain electrode of the first PMOS transistor and the grid electrode of the second PMOS transistor are connected to the output terminal of a first control signal; the grid electrode of a third PMOS transistor and the source electrode of the second NMOS transistor are connected to the output terminal of a second control signal; the drain electrode of the first NMOS transistor is connected to the drain electrode of the third PMOS transistor, the grid electrode of the first NMOS transistor and the second NMOS transistor; and the source electrode is connected to the ground through a second resistor. The beneficial effect is that the load power consumption is reduced when the power is switched off, the current is reduced when the power is switched off, and the impact on the service life of members caused by big current is reduced.

Description

technical field [0001] The invention relates to a circuit capable of reducing load power consumption when the power supply is turned off. Background technique [0002] In smart electronic devices such as PCs, portable computers, tablet computers, and smart phones, when the power is turned off, the circuit needs to do a lot of storage and preparation work. At this time, the power consumption of the circuit is generally large. It will increase accordingly, so it will cause a certain degree of instability to some electronic components and shorten the life of these electronic components. Contents of the invention [0003] The object of the present invention is to provide a circuit capable of reducing load power consumption when the power supply is turned off in view of the above existing problems. [0004] The technical solution adopted by the present invention is as follows: a circuit for reducing load power consumption when the power supply is turned off, the circuit includ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/687
Inventor 王纪云吴勇王晓娟
Owner ZHENGZHOU DANDIAN TECH SOFTWARE
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