Building sample rate independent timing diagrams using digital edge averaging

Abstract

The invention relates to building sample rate independent timing diagrams using digital edge averaging. A method can include receiving an input signal having multiple signal edges, performing an initial scan of the input signal to identify peaks corresponding to the signal edges, and determining whether each peak is a Uniformly Synchronous (US) edge or a Quasi-Synchronous (QS) edge. The method can also include generating a final waveform and displaying the final waveform on a display device.

Description

Background technique [0001] Digital acquisition devices such as the Tektronix TLA7000 logic analyzer enable electrical engineers to measure the signals generated by the digital systems they design. The research laboratory uses digital acquisition devices to observe the correctness of timing and signal density in the microprocessor, memory, bus, and other components of the digital system. The acquisition device plays an important role in continuing to promote the development of the electronics industry. [0002] The digital acquisition device generally displays the sensed signal in a steeply rising or falling staircase form. The rise from "off" to "on" and the fall from "on" to "off" are usually synchronized with the clock cycle in the system under test, and the transition from one state to another is visually represented as vertical edge. It is useful to distinguish the clock of the system under test from the clock of the digital acquisition device. [0003] In order to provide ...

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