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Binary image lossless compression and decompression IP core based on FPGA and application

A binary image, lossless compression technology, applied in the direction of image communication, electrical components, etc., can solve the problem of occupying more CPU resources, achieve good compression effect, fast decompression speed, and good application prospects

Inactive Publication Date: 2014-05-14
XIDIAN UNIV
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  • Claims
  • Application Information

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Problems solved by technology

With the improvement of the resolution of the output device, the amount of data per page of the document is also increasing. For example, a page of A4 document with 600*1200DPI requires about 8M memory capacity. Therefore, in order to increase the number of cached document pages, it is necessary to The printer controller supports lossless data compression and decompression of binary images. Although it is relatively easy to implement compression and decompression using programs, it requires more CPU resources and puts forward higher requirements for embedded system design.

Method used

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  • Binary image lossless compression and decompression IP core based on FPGA and application

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Embodiment Construction

[0020] Please refer to figure 1 , an FPGA-based binary image lossless compression and decompression IP core and its application.

[0021] An FPGA-based binary image lossless compression and decompression IP core, which includes,

[0022] a register, the register is used to store binary image data;

[0023] FIFO unit, the FIFO unit is used to read the binary image data in the register;

[0024] MR compression module, the compression module reads the original binary image data in the register through the FIFO unit, and compresses the original binary image data read;

[0025] MR decompression module, the decompression module reads the compressed binary image data in the register through the FIFO unit, and decompresses the read compressed binary image data. The MR compression module is implemented by VHDL language, wherein the MR code is a two-dimensional code, the first line of the MR code adopts MH code, and the second line of the MR code is compressed according to the data o...

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Abstract

The invention relates to a binary image lossless compression and decompression IP core based on an FPGA. The binary image lossless compression and decompression IP core based on the FPGA comprises a register used for storing binary image data, an FIFO unit used for reading the binary image data in the register, an MR compression module which reads the original binary image data in the register through the FIFO unit and compresses the read original binary image data, and an MR decompression module which is used for reading the compressed binary image data in the register through the FIFO unit and decompressing the read compressed binary image data. The binary image lossless compression and decompression IP core based on the FPGA has the advantages of being good in binary image compression effect and high in compression and decompression speed. The binary image lossless compression and decompression IP core based on the FPGA can achieve a good application prospect in G3 equipment, G4 equipment and the application technology field.

Description

technical field [0001] The invention relates to an FPGA-based binary image lossless compression and decompression IP core and its application. Background technique [0002] Currently, most printers, fax machines, and all-in-ones are still binary devices. When processing and printing document data, in order to realize multi-copy printing and copying functions, all documents need to be buffered inside the printer. With the improvement of the resolution of the output device, the amount of data per page of the document is also increasing. For example, a page of A4 document with 600*1200DPI requires about 8M memory capacity. Therefore, in order to increase the number of cached document pages, it is necessary to The printer controller supports lossless data compression and decompression of binary images. Although it is relatively easy to implement compression and decompression using programs, it needs to occupy more CPU resources, which puts forward higher requirements for embedd...

Claims

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Application Information

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IPC IPC(8): H04N1/41H04N1/00
Inventor 田玉敏王泉白长昊潘静雅刘锦辉
Owner XIDIAN UNIV
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