Method for Optimizing the Morphology of Metal Silicide at the Bottom of Self-Aligned Contact Hole

Abstract

The invention discloses a method for optimizing the morphology of metal silicide at the bottom of a self-aligned contact hole. According to the method, the following steps are performed after a contact hole is formed by etching and before a metal barrier layer is grown: (1) a silicon oxide protection layer is grown on the surface of a substrate loss region; (2) fast thermal annealing treatment is performed with nitrogen and hydrogen; and (3) silicon oxide at the bottom of the contact hole is removed. According to the method, as a silicon oxide protection layer is formed on the side wall of the substrate loss region, formation of irregular silicide extension due to reaction between metal Ti in the barrier layer and Si on the side wall of the substrate loss region is avoided when a self-aligned contact hole is formed, thus ensuring the performance of semiconductor devices.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for optimizing the morphology of metal silicide at the bottom of a self-aligned contact hole. Background technique [0002] Metal silicide (silicide) is an indispensable and important process method in semiconductor technology, and it has important uses in reducing hole resistance, contact resistance and improving the speed of MOS devices. In the formation of self-aligned contact hole (SAC-LIC), through the chemical reaction between metal Ti and silicon substrate, we can get TiSi 2 This most commonly used metal silicide. In order to ensure good contact between the contact hole and the substrate (sub), a certain amount of substrate loss (silicon loss) is generally left at the bottom of the hole, and it is this substrate loss that allows the silicon at the bottom of the contact hole to form sidewalls. However, in the existing manufacturing process, there i...

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Problems solved by technology

However, in the existing manufacturing process, there is no protective structure for silicon on this sidewall, so the sidewall will react with metal Ti

In some extreme abnormal cases, the reaction between Ti and Si sidewall is out of control, and the silicide region will extend irregularly in the horizontal direction, such as figure 1 As shown, this will cause abnormal performance of MOS devices, such as figure 2 As shown, the two curves of ID and IB coincide, that is, the currents of ID and IB are equal, and the leakage path is from the drain of the device to the substrate, indicating that the entire circuit is ineffective.

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