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Promotion of partial data segments in flash cache

A partial data and high-speed cache technology, applied in the computer field, can solve the problems of secondary cache storage space waste, resource consumption, and performance degradation

Active Publication Date: 2014-07-02
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In data processing systems with multiple levels of cache, it can be challenging to write so-called "partial tracks", or pieces of data that are not completely full, to the secondary cache
For example, storage space on the secondary cache may be wasted
In a secondary cache implemented as flash or flash cache, memory is typically costly to implement and wasted storage space can consume scarce resources
Furthermore, returning to the disk drive or other primary storage to collect additional data to fill "holes" in some tracks may cause additional input / output (I / O) activity, also consuming resources and potentially degrading performance

Method used

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  • Promotion of partial data segments in flash cache
  • Promotion of partial data segments in flash cache
  • Promotion of partial data segments in flash cache

Examples

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Embodiment Construction

[0016] For purposes of illustration, the term "secondary cache" is used to refer to any cache (including, for example, L2 or L3 cache) that resides between a primary cache and a storage device, such as a disk drive, tape drive, or the like.

[0017] refer to figure 1 , illustrates one embodiment of a computer-network architecture 100 . Architecture 100 is presented to illustrate various scenarios for implementing the caching system illustrated herein. Architecture 100 is presented by way of example only and not limitation. Indeed, in addition to the illustrated network architecture 100, the caching system disclosed herein is applicable to a wide variety of different computer, server, storage system, and network architectures.

[0018] As shown, the computer-network architecture 100 may include one or more computers 102 , 106 interconnected by a network 104 . The network 104 may include, for example, a local area network (LAN) 104, a wide area network (WAN) 104, the Internet...

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PUM

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Abstract

Exemplary method, system, and computer program product embodiments for efficient track destage in secondary storage in a more effective manner, are provided. In one embodiment, by way of example only, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage. Additional system and computer program product embodiments are disclosed and provide related advantages.

Description

technical field [0001] The present invention relates generally to computers and, more particularly, to mechanisms for promoting portions of data fragments in computing storage environments. Background technique [0002] In today's society, computer systems are very common. In computing, "cache" generally refers to a small, fast memory or storage device used to store recently accessed, frequently accessed, or likely to be accessed data or instructions in the future. Reading from or writing to a cache is typically less expensive (in terms of access time and / or resource utilization) than accessing other memory or storage devices. Once data is stored in the cache, it can be accessed in the cache rather than refetching and / or recomputing the data, saving time and resources. [0003] The cache may be provided as a multi-level cache. For example, a cache system may include a "primary" cache and a "secondary" cache. When reading data, a computing system or device may first look ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG06F12/128G06F2212/283G06F12/0864G06F12/0897G06F2212/222G06F12/0253G06F2212/1016G06F12/0246G06F12/122G06F2212/702G06F2212/7201G06F12/0871G06F12/0862G06F12/127G06F12/0811G06F3/0619G06F3/0646G06F3/0688G06F2212/154G06F2212/604
Inventor L·M·古普塔E·S·埃勒夫塞里奥I·科尔特斯达斯胡晓宇R·普勒特卡R·哈斯S·布利尼克M·J·卡洛斯K·A·内尔森M·T·本哈斯
Owner IBM CORP