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Integrated circuit high-voltage pin connectivity testing method

A technology of connectivity testing and high-voltage pins, which is applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problems that high-voltage pins cannot be tested, and achieve the effect of complete mid-test technology

Active Publication Date: 2014-08-06
ZHEJIANG WUXIAN NEW ENERGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] At present, in the field of integrated circuit testing, only the low-voltage pins can be tested for the connectivity between the probe card and the chip, and the high-voltage pins cannot be tested.

Method used

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  • Integrated circuit high-voltage pin connectivity testing method
  • Integrated circuit high-voltage pin connectivity testing method
  • Integrated circuit high-voltage pin connectivity testing method

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Embodiment Construction

[0017] In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0018] figure 1 A flow chart of a method for testing the continuity of an integrated circuit high-voltage pin according to the present invention is shown.

[0019] refer to figure 1 ,Such as figure 1 As shown, a method for testing the continuity of an integrated circuit high voltage pin comprises the following steps:

[0020] S1, except for the pin port PIN to be tested connected to the MOS tube substrate body inside the integrated chip, all other pin port PINs are grounded;

[0021] S2, apply a negative current to the port PIN to be tested, and test its ground voltage V.

[0022] The step ...

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Abstract

The invention discloses an integrated circuit high-voltage pin connectivity testing method. The method includes the following steps: enabling other pin ports PIN with the exception of a to-be-tested pin port PIN of an MOS (metal oxide semiconductor) field effect transistor substrate body connected inside an integrated chip to be grounded; applying negative current on the to-be-tested pin port PIN to test voltage to ground V of the to-be-tested pin port PIN. By the method, testing of connectivity of a chip high-voltage pin can be completed, and middle testing technology of an integrated circuit is enabled to be more complete.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to a method for testing the connectivity of high-voltage pins of integrated circuits. Background technique [0002] At present, in the field of integrated circuit testing, only low-voltage pins can be tested for the connectivity between the probe card and the chip, but high-voltage pins cannot be tested. [0003] ESD is the abbreviation of Electro-Static discharge, which means "electrostatic discharge". [0004] PAD refers to the input and output ports of the entire chip, and is an interface to be connected to the external packaging frame (bonding frame). [0005] Usually, low-voltage pins have ESD circuits for power and ground. With the help of these ESD protection diodes, the ESD circuit structure is as follows: figure 1 shown. The circuit between PAD and VDD is equivalent to a forward diode, between PAD and VSS is equivalent to a reverse diode, inject positive / negativ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/02
Inventor 刘成军
Owner ZHEJIANG WUXIAN NEW ENERGY
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