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Floating point constant generation instruction

A floating-point and instruction technology, applied in electrical digital data processing, instruments, calculations, etc., can solve problems such as increasing code size and increasing waiting time

Inactive Publication Date: 2014-10-15
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As can be appreciated, such conventional techniques for generating floating point constants result in increased latency, increased code size, and / or increased hardware

Method used

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  • Floating point constant generation instruction
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Embodiment Construction

[0016] Several aspects of the invention are disclosed in the following description and related drawings directed to specific embodiments of the invention. Alternative embodiments may be devised without departing from the scope of the present invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.

[0017] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments of the invention" does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the invention. ...

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Abstract

Systems and methods for generating a floating point constant value from an instruction are disclosed. A first field of the instruction is decoded as a sign bit of the floating point constant value. A second field of the instruction is decoded to correspond to an exponent value of the floating point constant value. A third field of the instruction is decoded to correspond to the significand of the floating point constant value. The first field, the second field, and the third field are combined to form the floating point constant value. The exponent value may include a bias, and a bias constant may be added to the exponent value to compensate for the bias. The third field may comprise the most significant bits of the significand. Optionally, the second field and the third field may be shifted by first and second shift values respectively before they are combined to form the floating point constant value.

Description

technical field [0001] The disclosed embodiments relate to floating point arithmetic. More specifically, the exemplary embodiments relate to instructions for generating commonly used floating point constants. Background technique [0002] Floating-point representations of numbers are useful in systems for computing that support a wider range of values ​​than can be supported by the available integer or fixed-point formats. In floating point numbers, the decimal point (decimal / binary) is allowed to be "floating", which makes it possible to encode a wide range of values ​​using a small number of bits. Due to the wide range, many floating point numbers may not be efficiently representable in fixed point format without severe loss of precision or sometimes errors / anomalies. [0003] Some modern processors support floating-point instructions that operate on numbers represented in floating-point format. Integrating floating point instructions in integer / fixed point processor pi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30
CPCG06F9/30025G06F9/30014G06F9/30167G06F9/30032
Inventor 埃里希·詹姆士·普罗恩德克鲁西恩·科德雷斯库查尔斯·约瑟夫·塔伯尼斯瓦米纳坦·巴拉苏布拉马尼安
Owner QUALCOMM INC