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Chip arrangement method for improving chip simultaneous testing

A chip and chipset technology, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problems of long test time, difficult to make probe cards, long test time, etc., and achieve the effect of reducing test costs

Active Publication Date: 2017-08-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the test time will become longer and longer, and the probe card will become more and more difficult to manufacture, because the probes will not be able to arrange pins if the spacing is too small
[0003] In addition, in the case of small chips, the difficulty of making probe cards is generally reduced by reducing the number of simultaneous tests, but this also makes the test time longer.

Method used

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  • Chip arrangement method for improving chip simultaneous testing
  • Chip arrangement method for improving chip simultaneous testing
  • Chip arrangement method for improving chip simultaneous testing

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Embodiment Construction

[0021] The chip arrangement method for improving chip simultaneous testing of the present invention comprises the steps of:

[0022] 1) Place the chip on the silicon wafer according to the mapping method (such as the symmetrical rotation method) (such as figure 2 shown);

[0023] 2) Connect the PADs of adjacent chips together to form a chipset, for example, as image 3 As shown, through the connection of two chips, the two chips are combined into a chipset;

[0024] 3) The probe card only needs to use the chip set connected together as a whole chip (large chip), and when the probe pricks the needle, only one of the chips in the chip set that constitutes step 2) is pricked;

[0025] 4) Set the address lines of each chip in a chipset to different levels, and the chip address lines are connected to different connections (that is, the chip address lines are connected in different ways);

[0026] 5) Send different instructions through different address information of the chip (...

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Abstract

The invention discloses a chip arrangement method for improving chip simultaneous testing, including: 1) placing the chips on the silicon chip in a mapping manner; 2) connecting the PADs of adjacent chips together to form a chip group ;3) When the probe pricks the needle, only pierce one of the chips in the chipset that constitutes step 2); 4) Set the address line of each chip in a chipset to a different level; 5) Through different addresses of the chips Information, to test the different chips that make up the same chipset; 6) By dicing, cut and separate the connecting lines in the dicing groove to form independent chips. The invention can solve the difficult problem of making small-chip probe cards, increase the number of simultaneous testing of small-chip silicon chips, improve test efficiency, reduce test cost, and the like.

Description

technical field [0001] The invention relates to a method for arranging chips in the field of semiconductors, in particular to a method for arranging chips for improving simultaneous testing of chips. Background technique [0002] With the development of chip technology, the number of chips on a silicon wafer is increasing and smaller. However, the way traditional chips are placed in silicon wafers, such as figure 1 As shown, it is all in one direction. Therefore, the test time will become longer and longer, and the probe card will become more and more difficult to manufacture, because the pin spacing will not be able to arrange pins if the probes are too small. [0003] In addition, in the case of small chips, the difficulty of making probe cards is generally reduced by reducing the number of simultaneous tests, but this also makes the test time longer. Contents of the invention [0004] The technical problem to be solved by the present invention is to provide a method ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/00
Inventor 武建宏
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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