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Asynchronous chip simultaneous test method

An asynchronous, chip technology, used in digital circuit testing, electronic circuit testing, etc., can solve the problems of small number of simultaneous tests and long data processing time, and achieve the effect of increasing the number of simultaneous tests, saving test costs, and shortening test time.

Active Publication Date: 2008-04-23
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology

like figure 1 As shown, when the three asynchronous chips are tested at the same time, firstly, the three chips accept the command synchronously. Since the responses of the asynchronous chips cannot appear at the same time, wait for a period of time after the command is sent, and the responses within the allowable time period All the data is collected, and finally, the data of each chip is analyzed offline to judge whether it is qualified or not. The disadvantage is that the data processing time is relatively long, and the number of simultaneous measurements is relatively small.

Method used

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Embodiment Construction

[0011] First, match the first output of the asynchronous signal when testing multiple chips at the same time. For example, in the IS7816 protocol, when responding to 9000H, first match the "0" of the first clock output of the first start bit, such as figure 1 As shown, when chip 1 matches the first bit of data, the state of the test channel remains unchanged, mainly keeping the clock signal unchanged.

[0012] At this time, due to the stop of the clock signal, the chip 1 under test cannot output the next data. When the tester matches all the output first bit signals of chip 2, chip 3, and chip 4 within a certain period of time, it continues to run the test vector. Chips that have not been matched during this period of time will be treated as unqualified, while other matched chips have been kept in sync at this time, as long as they are compared sequentially.

[0013] If the product test of ISO7816 protocol communication is required, the synchronous control of multiple asynchr...

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Abstract

The method comprises: making match for the first bit instruction of the asynchronous signals of the chips under test; by control the clock signals of previously matched chip, making the multi asynchronous tested chips keep synchronous; continuously comparing the responded multi-bit instruction to realize the match for multi-bit asynchronous signals when realizing the match for the multi asynchronous tested chips.

Description

technical field [0001] The invention belongs to an integrated circuit test method, in particular to an asynchronous chip simultaneous test method. Background technique [0002] In the semiconductor testing industry, existing memory testers can only match one bit of data, and cannot perform simultaneous testing if multiple bits of data are to be matched. [0003] The logic tester is to take out all the data of multiple chips in a certain period of time, and then analyze and process the data. Such as figure 1 As shown, when the three asynchronous chips are tested at the same time, firstly, the three chips accept the command synchronously. Since the responses of the asynchronous chips cannot appear at the same time, wait for a period of time after the command is sent, and the responses within the allowable time period All the data is collected, and finally, the data of each chip is analyzed offline to judge whether it is qualified or not. The disadvantage is that the data pro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R31/317
Inventor 武建宏黄海华
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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