A Partial Triple-Mode Redundancy Method Based on Lookup Table Configuration Bit Statistics

Abstract

The invention discloses a partial triplication redundancy method based on lookup table configuration bit statistics. The method includes the steps: S1, mapping a circuit to be subjected to redundancy into k, inputting a lookup table format, reading information of the circuit to be subjected to redundancy, and setting up a circuit topological structure database; step S2, subjecting circuit topological structure information to statistics, and recording unrelated configuration bit information of each node in the circuit to be subjected to redundancy; step S3, acquiring single event effect sensitivity information of the lookup table according to the number of the unrelated configuration bit; step S4, extracting a single event upset-sensitivity lookup table from single event effect sensitivity information of the lookup table, subjecting the single event upset-sensitivity lookup table to triplication redundancy to obtain redundancy results, and inserting a voter between each redundancy module and a non-redundancy module according to the redundancy results so as to construct a partial triplication redundancy circuit resistant to single event effects. The partial triplication redundancy method based on lookup table configuration bit statistics has the advantages that system reliability can be greatly improved, and about half of hardware cost of a full triplication redundancy circuit can be saved.

Description

technical field [0001] The invention relates to the technical field of digital system fault tolerance, in particular to a method for reducing hardware overhead in the triple-mode redundancy technology of programmable devices. technical background [0002] Programmable device (FPGA) has the characteristics of short development cycle, low cost, and high flexibility, so it is widely used in electronic system design. The FPGA chip based on static random access memory (SRAM) configuration depends entirely on internal configuration data. , according to the existing literature and in-orbit flight data, SRAM-type FPGA devices are mainly susceptible to Single Event Upset (SEU) in the space radiation environment, so the design of SRAM-based FPGA systems should focus on SEU protection. [0003] Figure 1a Shown is a schematic diagram of the circuit to be redundant, Figure 1b Shown is a schematic diagram of the full three-mode redundant circuit. Such as Figure 1a The circuit to be ...

AI Technical Summary

Problems solved by technology

[0007] Since the sensitivity of the existing technology is calculated based on the gate-level circuit structure and input probability, the fault tolerance effect and overhead savings are greatly reduced after it is mapped to the FPGA structure based on the lookup table

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