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A method and filtering device for realizing FIR filtering

A filter and filter coefficient technology, applied in the field of FIR filtering, can solve problems such as waste of FPGA resources

Active Publication Date: 2018-05-11
CHINA MOBILE GRP GUANGDONG CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a method and a filtering device for realizing FIR filtering. In the prior art, the working frequency of the FIR filter is always much higher than the data input rate of the FIR filter. Bit registers are a big waste of FPGA resources

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  • A method and filtering device for realizing FIR filtering

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Embodiment Construction

[0020] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

[0021] In the present invention, utilize the clock frequency of the FIR filter in the FPGA to be higher than the characteristics of the data input rate of the FIR filter, the RAMs in the FPGA are cascaded, and the changes of the read and write addresses of each RAM and the write enable are used to realize the internal data of each RAM. Selective write and read, realize the output of FIR filter delay data. Wherein, the clock period of the FIR filter can be calculated according to the clock frequency of the FIR filter.

[0022] An embodiment of the present invention provides a method for implementing FIR filtering, such as figure 1 As shown, applied to FPGA, the methods include:

[0023] Step 101, cascading α RAMs on the FPGA, and connecting each RAM wit...

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Abstract

Embodiments of the present invention provide a method and a filtering device for realizing FIR filtering, cascading α RAMs of the FPGA, and connecting each RAM to the FIR filter; setting a multiplexing cycle to include multiple clock cycles, and each RAM in A delayed data is output in different clock cycles of the multiplexing cycle, and the delayed data participates in the filtering operation in the FIR filter, and the delayed data output by the first (α‑1) RAMs are allowed to be input into the next RAM in the cascade respectively; In the filtering operation, when the FIR filter coefficients of at least two delayed data are the same, at least two delayed data are added to obtain a delayed sum value, the delayed sum value is multiplied by the FIR filter coefficient to obtain a product, and all products are The summation obtains the filtering result of the current multiplexing cycle. The filtering operation is to add at least two delayed data and then perform multiplication to obtain a product, thus reducing the number of multiplier units performing multiplication.

Description

technical field [0001] The present invention relates to FIR filtering technology, in particular to a method and filtering device for realizing FIR filtering. Background technique [0002] In digital intermediate frequency processing technology, FIR filter is an indispensable and important part. A large number of FIR filters are realized by FPGA and other devices. The mathematical equation of FIR filter is In the implementation process, it is necessary to delay the input data and obtain N delay data of the filter order for calculation. Mostly, the IP CORE generation tool is used to generate a shift register to realize the delay. [0003] The shift register generated by the development tool is a general-purpose device, which is not optimized according to the operation method and structural characteristics of the FIR filter, and is suitable for use when the filter order is low. [0004] The existing technology has the following problems: when the order of the filter is high, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03H17/02
Inventor 刘少聪
Owner CHINA MOBILE GRP GUANGDONG CO LTD
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