Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

FIR filtering realization method and filtering device

A filter and filter coefficient technology, applied in the field of FIR filtering, can solve problems such as waste of FPGA resources

Active Publication Date: 2015-02-11
CHINA MOBILE GRP GUANGDONG CO LTD
View PDF3 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a method and a filtering device for realizing FIR filtering. In the prior art, the working frequency of the FIR filter is always much higher than the data input rate of the FIR filter. Bit registers are a big waste of FPGA resources

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • FIR filtering realization method and filtering device
  • FIR filtering realization method and filtering device
  • FIR filtering realization method and filtering device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0020] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

[0021] In the present invention, utilize the clock frequency of the FIR filter in the FPGA to be higher than the characteristics of the data input rate of the FIR filter, the RAMs in the FPGA are cascaded, and the changes of the read and write addresses of each RAM and the write enable are used to realize the internal data of each RAM. Selective write and read, realize the output of FIR filter delay data. Wherein, the clock period of the FIR filter can be calculated according to the clock frequency of the FIR filter.

[0022] An embodiment of the present invention provides a method for implementing FIR filtering, such as figure 1 As shown, applied to FPGA, the methods include:

[0023] Step 101, cascading α RAMs on the FPGA, and connecting each RAM wit...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The embodiment of the invention provides an FIR filtering realization method and a filtering device. Alpha RAMs of an FPGA are cascaded, and all the RAMS are connected with an FIR filter; a reuse cycle comprising multiple clock cycles is arranged, each RAM outputs one delay data in different clock cycles of the reuse cycle, the delay data participates in filtering operation in the FIR filter, and the delay data outputted by anterior (alpha-1) RAMs are permitted to be respectively inputted to the next cascaded RAM; and in filtering operation, when coefficients of the FIR filter of at least two delay data are identical, the at least two delay data are added and a delay sum value is obtained, the delay sum value and the coefficients of the FIR filter are multiplied and a product is obtained, and all the products are added so that the filtering result of the current reuse cycle is obtained. Filtering operation is that at least two delay data are added and then multiplication operation is performed and the product is obtained so that the number of multiplier units performing multiplication operation is reduced.

Description

technical field [0001] The present invention relates to FIR filtering technology, in particular to a method and filtering device for realizing FIR filtering. Background technique [0002] In digital intermediate frequency processing technology, FIR filter is an indispensable and important part. A large number of FIR filters are realized by FPGA and other devices. The mathematical equation of FIR filter is In the implementation process, it is necessary to delay the input data and obtain N delay data of the filter order for calculation. Mostly, the IP CORE generation tool is used to generate a shift register to realize the delay. [0003] The shift register generated by the development tool is a general-purpose device, which is not optimized according to the operation method and structural characteristics of the FIR filter, and is suitable for use when the filter order is low. [0004] The existing technology has the following problems: when the order of the filter is high, ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H03H17/02
Inventor 刘少聪
Owner CHINA MOBILE GRP GUANGDONG CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com