Microprocessor micro system structure parameter optimization method based on Petri network

Abstract

The invention discloses a microprocessor micro system structure parameter optimization method based on a Petri network. The method comprises the following steps that a template of a flow line model is built on the basis of the colored Petri network, an instruction sequence of a target application program is obtained, relevant information between the instructions and the function unit types is obtained, a colored Petri network model, running under the current parameter configuration, of the target program is generated, a Petri network simulation tool is used for simulation, a simulation report is generated, the colored Petri network model is used for generating a corresponding directed acyclic graph according to the simulation report, a key path of the directed acyclic graph and nodes passed by the key path are calculated, the release time of each entering edge of each node is calculated, the performance bottle neck or power consumption bottle neck for running the target application program by the microprocessor in the current micro system structure parameter configuration is analyzed, and if the optimization is required, the micro system structure parameters are regulated. The microprocessor micro system structure parameter optimization method has the advantages that the prediction reliability and the precision are high, the searching design space relating range is wide, the optimization algorithm complexity is lower, and the optimization is fast and efficient.

Description

technical field

[0001] The invention relates to a microprocessor performance bottleneck analysis and optimization method in the technical field of microprocessor design, in particular to a microprocessor microarchitecture parameter optimization method based on colored Petri nets. Background technique

[0002] In the early stage of microprocessor design, the details of the microprocessor microarchitecture must first be determined, including: the number of pipeline stages, the number of registers between pipeline stations, and the number of key resources, such as reorder buffers (Reorder buffer) size, the size of the commit queue, etc., the number of execution units, delay, value width, emission width, in-order execution or out-of-order execution, etc. How to choose these parameters at the initial stage of design is very challenging work. The choice of parameters depends on the characteristics of the application that the processor is oriented to. It is necessary to conduct a ...

Examples

Embodiment Construction

[0071] Such as figure 1 As shown, the implementation steps of the microprocessor microarchitecture parameter optimization method based on Petri net in this embodiment are as follows:

[0072] 1) According to the microarchitecture of the microprocessor, the template of the pipeline model is constructed based on the colored Petri net.

[0073] Such as figure 2 In the abstract diagram of the superscalar pipeline shown, the pipeline includes 6 pipeline segments, which are fetch, decode, rename, issue, execute (exe) and write Back (commit), where the execution (exe) includes 2 arithmetic logic units (ALU), 1 floating point unit (FP), and 1 memory access unit (load / store). The pipeline model is to describe the structure of such a pipeline. The template of the pipeline model describes the structure of the pipeline, the number of various resources in the pipeline, resource competition and arbitration, etc. In this embodiment, the storage space, the quantity and type of various res...

technical field

[0001] The invention relates to a microprocessor performance bottleneck analysis and optimization method in the technical field of microprocessor design, in particular to a microprocessor microarchitecture parameter optimization method based on colored Petri nets. Background technique

[0002] In the early stage of microprocessor design, the details of the microprocessor microarchitecture must first be determined, including: the number of pipeline stages, the number of registers between pipeline stations, and the number of key resources, such as reorder buffers (Reorder buffer) size, the size of the commit queue, etc., the number of execution units, delay, value width, emission width, in-order execution or out-of-order execution, etc. How to choose these parameters at the initial stage of design is very challenging work. The choice of parameters depends on the characteristics of the application that the processor is oriented to. It is necessary to conduct a ...

Examples

Embodiment Construction

[0071] Such as figure 1 As shown, the implementation steps of the microprocessor microarchitecture parameter optimization method based on Petri net in this embodiment are as follows:

[0072] 1) According to the microarchitecture of the microprocessor, the template of the pipeline model is constructed based on the colored Petri net.

[0073] Such as figure 2 In the abstract diagram of the superscalar pipeline shown, the pipeline includes 6 pipeline segments, which are fetch, decode, rename, issue, execute (exe) and write Back (commit), where the execution (exe) includes 2 arithmetic logic units (ALU), 1 floating point unit (FP), and 1 memory access unit (load / store). The pipeline model is to describe the structure of such a pipeline. The template of the pipeline model describes the structure of the pipeline, the number of various resources in the pipeline, resource competition and arbitration, etc. In this embodiment, the storage space, the quantity and type of various res...

Images