24 results about "Design space exploration" patented technology

The invention discloses a flash memory and near memory acceleration system of an end-side large language model, and belongs to the technical field of calculation, reckoning or counting. According to the system, a 3D NAND flash memory chip with near memory computing capability is adopted, and model weights and key value caches are uniformly stored in the flash memory. Storage-intensive operations involved in the big language model inference decoding stage are all completed in a logic layer of a flash memory, and an NPU only executes non-linear operations such as normalization and activation and residual connection; in the pre-filling stage, the NPU obtains weight and key value cache data from the flash memory and is used for completing all calculations. Redundant read-write is reduced through a flash memory page-level key value cache mapping mechanism; and meanwhile, attention head group parallel data stream optimization is provided, so that the parallelism of a decoding stage is improved. A discrete framework and a compact framework are further provided, and optimal configuration is automatically selected in combination with a design space exploration strategy. According to the method, the requirement of edge end large language model reasoning on the DRAM can be omitted, delay is reduced, throughput is improved, and system cost and power consumption are remarkably reduced.

The application discloses a kind of personalized design intelligent interaction methods based on topology optimization, including S1, construct the user behavior monitoring system based on multi-modal data acquisition, generate high-dimensional data set containing time sequence characteristics;S2, based on adaptive deep neural network model, dynamically predict and hierarchical modeling to user personalized demand;S3, the optimal solution of design parameter is generated in real time by dynamic topology reconstruction algorithm;S4, through reinforcement learning mechanism, iteratively update design scheme generation rule;S5, construct neural network supported multi-objective design space exploration and optimization framework, quickly filter and optimize design parameter;S6, through multidimensional data mapping and parameterization control means, realize the dynamic update and local optimization of design scheme;S7, establish data-driven continuous learning and evolution mechanism, constantly optimize user demand prediction model and design optimization algorithm.The application has the advantages of strong dynamic adaptability, high intelligent level and high personalized satisfaction precision.

The application discloses a method and device for efficient automatic power consumption optimization of chip physical design, solves the problem that the prior art cannot balance the time cost and optimization effect in design space exploration, realizes efficient exploration of high-dimensional continuous physical design parameters, and thus optimizes design parameters and reduces chip power consumption under the premise of guaranteeing design constraints; the method comprises the following steps: determining physical design parameters and boundaries based on a chip process node, sampling and constructing an initial data set; using a pre-trained large model to establish a small sample power consumption evaluation proxy model through context learning; parameter generation model iterative optimization: generating a candidate parameter combination, inputting the proxy model to obtain predicted power consumption, and updating model parameters until convergence according to the predicted power consumption; after training, the model generates a parameter combination to call an EDA tool to obtain real power consumption, so as to feed back the optimization model, and finally output a chip design with optimized power consumption.

The invention relates to a modeling and simulation method for a dynamic random access memory. According to the method, based on a target process node specified by a user, transistor and interconnection parameters are loaded from a process technical parameter database, and non-standard process node modeling is supported through an interpolation algorithm; the method comprises the following steps: performing top-down organization modeling on a dynamic random access memory by adopting a hierarchical structure, and introducing an H-type wiring network to describe address and data signal distribution; performing design space exploration on key physical parameters such as word line segmentation number, bit line segmentation number and column multiplexing degree to generate a plurality of physical implementation schemes; on the circuit level, the time delay, the power consumption and the area are accurately calculated by utilizing an analytical model, and specific time sequence parameters and refresh power consumption evaluation of the dynamic random access memory are integrated; and finally, selecting an organization scheme with the optimal comprehensive performance according to a multi-objective optimization criterion. According to the method, different architecture schemes can be quickly and accurately evaluated in an early design stage, and effective support is provided for architecture optimization of the dynamic random access memory.

The invention discloses a Bayesian polynomial chaos neural network proxy model method, and belongs to the technical field of sandwich board structure optimization design and proxy models. The method comprises the following steps: firstly, determining structural composition, size association and design parameters of the Y-shaped sandwich panel, constructing an automatic modeling script file, and simulating a drop hammer impact experiment process; secondly, generating a data set required by optimization of the Y-shaped sandwich panel, completing preprocessing, determining a protection performance evaluation index and an optimization target, and generating effective sample data; thirdly, training the proxy model based on the training set and the verification set; finally, multi-objective optimization design is carried out, design space is explored, a Pareto solution set is obtained, and a comprehensive optimal solution is selected. Through cooperation of the high-precision efficient proxy model and the intelligent optimization algorithm, the design period is shortened, the design space exploration range is expanded, the energy absorption protection effect is remarkably improved while the light weight of the Y-shaped sandwich panel is achieved, and reference is provided for engineering application and optimization design of the Y-shaped sandwich panel.

The invention relates to the technical field of artificial intelligence of water conservancy and hydropower engineering, in particular to a thinking chain-based gravity dam design space feature extraction and data set creation method, which is used for collecting and integrating safety and evaluation data of a gravity dam and integrating an efficient and visual technical information platform to carry out design space exploration of a feature fusion algorithm. And the gravity dam is generated to improve the design performance and efficiency. In order to effectively utilize historical design experience, reduce data dimensionality and reduce data training amount, a design data set for thinking chain guidance is added in a data set, and design semantics in gravity dam design is converted into structured data representation by simulating a thinking chain process of a human designer. A data set capable of reflecting design decision logic and function-scheme relevance is constructed, and the requirement of subsequent generative design training can be met.

The application relates to the technical field of artificial intelligence for water conservancy and hydropower engineering, in particular to a gravity dam design space feature extraction and data set creation method based on a thinking chain, which collects and integrates safety and evaluation data of the gravity dam, integrates an efficient visual technology information platform to design a feature fusion algorithm design space, and generates the performance and efficiency of the gravity dam design. In order to effectively utilize historical design experience, reduce data dimension and reduce data training amount, design data sets for thinking chain guidance are added in the data set, the design semantics in the gravity dam design are converted into structured data representation through simulation of the thinking chain process of human designers, a data set capable of reflecting the design decision logic and function-scheme correlation is constructed, and the data set can support subsequent generative design training needs.

The invention relates to a mercuric chloride NPU operator automatic tuning method and system based on fusion operator performance modeling, and the method comprises the steps: firstly constructing an end-to-end performance analysis model of a fusion operator for collaborative execution of a Cube core and a Vector core, and employing two modes to accurately predict execution delays under different parameter configurations through dynamic discrimination of a calculation speed relation between double cores; on the basis, a heuristic design space exploration algorithm with minimization of data movement amount as guidance is provided, and the algorithm is combined with the multilevel storage characteristic of the mercuric chloride NPU, adopts a two-stage strategy of block size optimization and buffer area allocation collaboration, and automatically searches for optimal parameter configuration meeting on-chip storage capacity constraints. According to the method, automatic performance adjustment and optimization of the fusion operator are realized, compared with traditional manual adjustment and optimization or compiler default configuration, near-optimal configuration can be found within a few minutes, the average performance prediction error is lower than 5%, the maximum performance speed-up ratio of part of operators can reach 1.46 times, and the efficiency of operator development and deployment on the mercuric chloride NPU is remarkably improved.

The application discloses a micro-architecture design space exploration method based on deep learning, comprising: obtaining target processor micro-architecture parameters, constituting a design space, obtaining performance indicators of different design points in the design space, and dividing key modules based on the design points; creating a directed acyclic graph according to the key modules, constructing a prediction model using a graph attention network to obtain a parameter optimal solution in the directed acyclic graph that meets a design target; splicing the directed acyclic graph into a global graph to obtain interconnection parameters of the key modules, introducing federal learning to train a global prediction model, and predicting and evaluating performance data of the parameter optimal solution based on the global graph; and when the performance evaluation result meets a preset performance standard, outputting target configuration parameters of the target processor under each configuration dimension. The application performs micro-architecture design space exploration in a graph embedding space, provides decision support for chip design, and improves design efficiency and flexibility by taking the idea of coordination between different design stages and design modes.

The application discloses a hardware architecture and a design space exploration method for accelerating multi-channel convolution, comprising an external storage module, a preprocessing module, a cache module, a matrix multiplication module and an output dimension rearrangement module, the external storage module is connected to the preprocessing module, the preprocessing module is connected to the cache module, the cache module is connected to the matrix multiplication module, the matrix processing module is connected to the output dimension rearrangement module; a task level pipeline is formed among the preprocessing module, the cache module and the matrix multiplication module, and parallel processing of three tasks of matrixing of a feature map and a convolution kernel, intermediate value caching and matrix multiplication operation is realized. The application converts multi-channel convolution into matrix multiplication and accelerates the same through design of a hardware structure, simultaneously proposes a design space exploration method based on performance and execution time, maximally improves resource utilization, and efficiently realizes real-time calculation of multi-channel convolution.

The invention discloses an AUV (Autonomous Underwater Vehicle) frame fin rudder profile parameterization modeling method, which comprises the following steps of: firstly, constructing a global design parameter system comprising key geometric feature sizes including the chord length, the elongation, the sweepback angle and the thickness of a root tip of a fixed fin and the chord length, the elongation and the thickness of a movable control surface in three-dimensional modeling software; secondly, through a series of parameterized CAD feature operation, a fixed fin three-dimensional entity is constructed in sequence, and parts defined by control plane parameters are cut off from the fixed fin three-dimensional entity; subsequently, a three-dimensional entity of a movable control surface separated from the fixed fin is constructed within the resected portion, the size of which is also driven by the global parameters. When any global design parameter changes, the geometric model of the whole frame fin rudder can be updated automatically, accurately and coordinately, the design efficiency and flexibility of the AUV frame fin rudder are remarkably improved, systematic design space exploration and optimization are facilitated, and powerful technical support is provided for rapid research and development and performance improvement of the AUV.

The present invention discloses a method for performing design space exploration, design optimization, and fine-tuning of analog circuits using a machine learning (ML) model. The method includes designing a base analog circuit, collecting SPICE simulation data for a random number of combinations of input, output, and process, voltage and temperature conditions, generating the data set from the simulation results, training the ML model using the generated dataset, identifying dominant circuit components in the base analog circuit configuration using Pearson correlation coefficients, generating from the trained machine learning model, a group of candidate analog circuit designs based on boundary conditions and desired specifications, and from the group of candidates calculating the candidate circuit that meets all the optimization criteria and the boundary conditions. The method further includes fine-tuning the optimized circuit by re-optimizing it for one or more specific sets of input, output, or PVT conditions to bring its specifications to the desired values.

The invention discloses a light source and mask collaborative optimization system and method based on a large language model, and the system comprises a user agent module, a control module, a design space exploration module, a script generation module, a light source optimizer and a mask optimizer. The analysis module is used for analyzing an optimization demand input by a user by utilizing a large language model and converting the optimization demand into an executable optimization task and a constraint condition; the control module is used for judging the type of an optimization task, decomposing the optimization task into a plurality of task series according to the type of the optimization task, and distributing the task series to the corresponding modules for processing; the design space exploration module is used for generating various optimization design parameter groups according to optimization tasks and constraint conditions; and the script generation module is used for generating a script file suitable for the light source optimizer and / or the mask optimizer by utilizing a large language model according to the various optimization design parameter combinations. The technical scheme of the invention has the advantages of good interactivity and high optimization efficiency.

The invention discloses a large language model training method and an HLS design space exploration method and device.According to the large language model training method and device, an HLS knowledge corpus, a result quality reverse reasoning corpus, an instruction scheduling forward reasoning corpus and a Pareto frontier reasoning corpus are constructed, and three-layer progressive training is conducted on a large language model based on the constructed corpus; therefore, the large language model is not only a simple instruction generator any more, but has the complete optimization reasoning capability of diagnosing the HLS design bottleneck, analyzing the result quality influence, formulating a fine-grained instruction scheduling strategy, and carrying out macroscopic Pareto frontier exploration planning and multi-target tradeoff; by means of the method, a large language model can understand the complex relation between optimization instruction configuration and result quality information more deeply, and intelligent reasoning can be conducted on the basis of understanding an HLS optimization strategy.

The invention discloses a double-sided three-dimensional stacked transistor standard cell layout generation method, which comprises the following steps of: applying a multi-row relative position constraint and a separation grid constraint to a transistor through a multi-row layout design and field region merging insertion, and applying a merging structure lower limit constraint to double-sided wire nets of N-type and P-type field effect transistors; the layout of the double-sided transistors is obtained through two times of solving, so that each double-sided wire net can complete wiring by combining the wire nets; in a wiring stage in the double-sided standard unit, a commodity flow conservation constraint and a design rule constraint are constructed, local iteration type wiring optimization is performed according to the obtained transistor layout and input / output pin front and back placement configuration and an initial solution, whether metal exists on edges connected with different nodes or not is obtained, and double-sided wiring is completed; and generating a double-sided three-dimensional stacked transistor standard cell layout. According to the invention, the area of the transistor standard cell can be optimized, and the flexible design space exploration capability is provided.

The embodiment of the application provides a space accelerator performance evaluation method in design space exploration, an electronic device and a computer storage medium, wherein the space accelerator performance evaluation method comprises the following steps: obtaining hierarchical array structure information of a space accelerator to be evaluated; determining a clock cycle number and a layout factor corresponding to the space accelerator according to the hierarchical array structure information, wherein the layout factor is used to represent the influence degree of the hierarchical array structure indicated by the hierarchical array structure information on the frequency of the space accelerator; and evaluating the performance of the space accelerator according to the clock cycle number and the layout factor. Through the embodiment of the application, the layout factor is used to replace the running frequency to evaluate the performance of the space accelerator, which can not only accurately evaluate the performance of the space accelerator, but also quickly and efficiently obtain the performance evaluation result, thereby improving the performance evaluation efficiency of the space accelerator as a whole and reducing the performance evaluation cost.

The embodiment of the application provides a design evaluation method and system based on design space exploration, electronic equipment and computer storage medium, wherein the design evaluation method based on design space exploration comprises the following steps: obtaining a design index corresponding to a system on chip to be evaluated; performing fuzzy logic reasoning on the design index through a fuzzy neural network model, and determining a structure parameter corresponding to the design index according to a reasoning result; and evaluating a design structure of the system on chip corresponding to the structure parameter to obtain an evaluation result. Through the embodiment of the application, the design of the SoC has interpretability.

The application relates to a micro-architecture design space exploration method and device, computer equipment, a storage medium and a computer program product, and relates to the technical field of Internet. The method comprises the following steps: obtaining design parameters in a micro-architecture design space of a target microprocessor; inputting the design parameters into a first model corresponding to each configuration dimension to obtain initial configuration parameters of the target microprocessor under each configuration dimension; inputting each initial configuration parameter into a task attention model to output corresponding parameter weights; fusing each parameter weight and each initial configuration parameter to obtain a correlation feature vector; and predicting target configuration parameters of the target microprocessor under each configuration dimension according to the correlation feature vector. The method can improve the accuracy of micro-architecture design space configuration prediction.

The application discloses a micro-architecture design space exploration method based on Gaussian mixture regression, adopts a Bayesian optimizer to realize incomplete supervised learning, can reduce the labeling cost of a data set, and accelerates the training of a model by utilizing prior probability, adopts a Gaussian mixture regression model as a proxy model, can simultaneously calculate the predicted mean of a target value and the covariance between multiple targets, compared with other models, can better perform multiple target optimization, uses a Bayesian information optimization criterion to determine the final number of Gaussian components, realizes the function of dynamically optimizing the number of Gaussian components, and makes the model better approximate a real function, collects a function CEIPV in combination with the target value, considers the balance problem between targets while providing the observation points with the highest uncertainty, and realizes the operation of selecting an optimal micro-architecture outside the data set by a conjugate gradient method.

The application discloses a design space exploration method, system and computer program product for micro-architecture. The method comprises: inputting a set of micro-architecture parameters of a target hardware, a value range of the parameters and a plurality of preset condition regions into a trained design point generation model, wherein the condition regions are preference regions divided from a predefined target space; generating a plurality of design points for each preset condition region according to the micro-architecture parameters and the value range thereof by using the trained design point generation model in a sequential decision manner, wherein a design point comprises all parameters and a set of values thereof; combining all generated design points, and performing a Pareto dominance relationship comparison to screen out a non-dominated solution set to form a Pareto front approximation. The application can quickly generate a high-quality, reasonable and interpretable Pareto front.

The application discloses a design space exploration method for cache hierarchy in a multi-core system. The method aims to optimize the cache subsystem in the multi-core system by reasonably configuring the cache hierarchy and the inter-chiplet network topology, thereby improving the system performance. The specific steps include: 1) cache miss rate and network delay modeling: modeling the cache miss rate and the network delay as functions of the cache hierarchy and the inter-chiplet network parameters; 2) optimization problem definition: defining the optimization target under the cost and power consumption constraints, and minimizing the concurrent average memory access time (C-AMAT); and 3) solving by a double-layer optimization algorithm: performing the cache subsystem optimization and the inter-chiplet network optimization by the double-layer optimization algorithm. The method provides an effective solution for the cache optimization of the multi-core system, and has a wide application prospect.

The invention discloses a configurable computing architecture based on subarrays, and belongs to the technical field of computing, reckoning or counting. Firstly, a hardware architecture capable of dynamically adjusting the scale and the connection mode of the sub-arrays is designed, and the utilization rate and the task adaptability of the PE array are improved; secondly, a design space exploration method is designed, the array scale can be determined according to the PE array utilization rate and the throughput rate, and the calculation efficiency is further improved. The computing architecture configurable scheme provided by the invention is relatively simple to apply, can effectively improve the hardware utilization rate and the system throughput rate, and is suitable for diversified neural network computing tasks.