46 results about "Design space exploration" patented technology

The present invention relates to a programmable device-based convolutional neural network acceleration method and system. The method comprises: designing a basic structure of a convolution neural network on the programmable device, and establishing the quantification model of the computing resource and the frequency about the parallelization parameter respectively; under different parallelization parameters, exploring the highest reachable clock frequency of the actual voltage, temperature, process deviation, establishing an analysis model of the actual highest reachable frequency and the parallelization parameter; and taking throughput calculation as an optimization purpose, according to the established quantitative model and analysis model, carrying out problem abstract on the convolutional neural network design space exploration, and using a certain search algorithm to solve the parallelization parameters with optimal performance. According to the method and system provided by the present invention, the delay margin reserved by the commercial design tools for the voltage, the temperature and the process deviation can be used while ensuring the stability and reliability of the accelerator, so that the performance of the convolutional neural network accelerator can be further improved.

A method for accelerating design space exploration of a target device when a behavioral description of the target device is given, includes: parsing the behavioral description to build a dependency parse tree; creating independent sets of clusters based on the dependency parse tree, each cluster being a set of a node or nodes of the dependency parse tree and independently explorable; exploring synthesizable operations of each cluster exhaustively in order to establish impact of each operation synthesized differently on a final circuit in designing of the target device; and combining attributes for the clusters to create designs with improved characteristics under constraints.

The time and computational resources needed to evaluate the potential input parameter settings in a design space is decreased by determining probabilities of improvement for input parameter settings in the design space and eliminating input parameter values that have low probabilities of improvement from the design space prior to compilation. The probability of improvement for input parameter settings is an estimate of the likelihood that the compilation of the user design using the set of input parameter settings will improve the performance of the user design with respect to one or more design goals, such as timing, power, or resource usage. The probability of improvement for input parameter settings can be determined from an analysis of the compilation results of sample designs, from attributes and/or constraints of the user design, and/or from a correlation between the results of optimization algorithms applied to the user design.

Design spaces for systems, including hierarchical systems, are programmatically validity filtered and quality filtered to produce validity sets and quality sets, reducing the number of designs to be evaluated in selecting a system design for a particular application. Validity filters and quality filters are applied to both system designs and component designs. Component validity sets are combined as Cartesian products to form system validity sets that can be further validity filtered. Validity filters are defined by validity predicates that are functions of discrete system parameters and that evaluate as TRUE for potentially valid systems. For some hierarchical systems, the system validity predicate is a product of component validity predicates. Quality filters use an evaluation metric produced by an evaluation function that permits comparing designs and preparing a quality set of selected designs. In some cases, the quality set is a Pareto set or an approximation thereof.

The invention discloses an FPGA-based YOLOv2-tiny neural network low-delay hardware accelerator implementation method. The method comprises the steps of network quantification; the overall hardware architecture design of the target detection system based on YOLOv2-tiny; design of a convolution layer processing unit; and double multiplier design and design space exploration. According to the invention, the time delay of the whole system can be significantly reduced, and the use efficiency of the DSP is improved.

The invention discloses an autonomous navigation system and an autonomous navigation method thereof based on a laser space communication transceiver. Based on the traditional laser space communication transceiver, a star capturing system is added, so that fixed stars and planets or satellites thereof can be recognized and the azimuth information can be obtained; by calculating the included angle among the fixed stars-space crafts-planets (or planets thereof), the position information of the space crafts can be obtained finally so as to achieve the navigation process. The laser space communication transceiver can obtain the navigation information without a set of additional autonomous navigation device, so that the relevant research, development, launch and running expense is saved, and the volume, weight and power consumption of the effective load of the aircrafts are reduced; the integral performance of the autonomous navigation system is improved; approximate real-time flight track correction is provided for deep space exploration according to the navigation result, so that not only can the signal round-trip delay between satellites and the ground be eliminated, but also ground data processing can be omitted.

The invention relates to a miniature solid-state power amplification device applied to deep-space exploration, and can be widely applied to various solid-state power amplification products for deep-space exploration. The solid-state power amplification device comprises a splitter, a DC/DC (direct current/direct current) power conversion circuit, a power switching circuit and a microwave amplification circuit. According to the miniature solid-state power amplification device, the DC/DC power conversion circuit is used for converting input primary power into voltage required by the microwave amplification circuit, and has the advantage of saving a larger space compared with a common mode of two paths of power; power supply to two microwave amplification links is switched through a dual-load relay; a GaAs MMIC (gallium arsenide monolithic microwave integrated circuit) chip design is adopted for integrally packaging the two microwave amplification links of the microwave amplification circuit, so that the requirements of reduction in weight and size are met; and the two microwave amplification links are backups of each other, so that the stability of the device is improved.

The invention relates to a simulation method of a Mars object for deep space exploration, which belongs to the field of deep space exploration application. In order to solve the problems in the prior art of lacking of a method for simulating the location, size, contour, imaging orientation and imaging gray level of Mars and existing technical gaps in engineering practices, the simulation method of the Mars object for deep space exploration is proposed. The simulation method includes transforming a center coordinate of Mars from a heliocentric ecliptic coordinate system to a display plane coordinate system and a projector coordinate system, calculating an imaging size of Mars according to an imaging field of view of a Mars explorer and the relative distance between Mars and the Mars explorer, simulating illuminated areas of Mars which are illuminated by the sun and unilluminated areas which are not illuminated by the sun, calculating an imaging orientation of the contour of Mars according to the relation of relative positions among the sun, Mars and the Mars explorer, and mapping a magnitude of Mars to the gray level of a computer to display on an interface. The simulation method of the Mars object for deep space exploration is applicable to the simulation software of deep space exploration.

A design space analyzer generates a parametric model associated with a design problem. The design space analyzer then discretizes various parameters associated with the model and generates a plurality of sample designs using different combinations of discretized parameters. The design space analyzer also computes one or more metrics for each sample design. In this fashion, the design space analyzer generates a coarse approximation of the design space associated with the design problem. The design space analyzer then evaluates portions of that approximation, at both global and local scales, to identify portions of the design space that meet certain feasibility criteria. Finally, the design space analyzer modifies the design space to facilitate more efficient exploration during optimization.

The invention provides a method and a device for generating X-frequency band one-way ranging signals for deep space exploration. The method provided by the invention can generate one-way ranging sidetone signals in the X-frequency band. The device provided by the invention comprises simulation devices such as a crystal oscillator, a frequency divider, a low-pass filter, a frequency multiplier, a phase shifter and the like, and turn-off of DOR (Differential One-way Ranging) sidetone signals can be controlled through an instruction. The crystal oscillator generates initial reference signals, one path of the initial reference signals are inputted into the frequency multiplier after power division, the frequency multiplier generates X-frequency band carriers, another path of the initial reference signals are inputted into a divide-by-two frequency divider, a left path of the initial reference signals are inputted into a divide-by-ten frequency divider, and two paths of DOR sidetone signals are generated respectively. Phase modulation is carried out on the two paths of DOR sidetone signals in the X-frequency band, and the two paths of DOR sidetone signals are outputted after being amplified and isolated. Divide-by-two frequency division and divide-by-ten frequency division are completed by a decimal counter. The X-frequency band one-way ranging signals generated by using the method provided by the invention can complete a function of accurate ranging for a deep space probe by being matched with relevant ground station equipment, thereby being applicable to the fields of lunar exploration, Mars exploration and the like.

The invention provides a lunar space exploration system based on the ladder principle. The lunar space exploration system is composed of a foundation, a foundation-space station cable, a space station, a balance weight-space station cable, a balance weight, a maintenance climbing device, fixed detectors and movable detectors. The foundation-station station cable is located above the foundation andthe bottom end of the foundation-station station cable is connected to the top end of the foundation; the space station is located above the foundation-station station cable and the bottom end of thespace station is connected to the top end of the foundation-station station cable; the balance weight-space station cable is located above the space station and the bottom end of the balance weight-space station cable is connected to the top end of the space station; the balance weight is located above the balance weight-space station cable, the maintenance climbing device is installed on the foundation-space station cable or the balance weight-space station cable; and the fixed detectors are fixed to the foundation-space station cable and the balance weight-space station cable in a scatteredmode, and the movable detectors are located inside the space station. According to the lunar space exploration system based on the ladder principle, large-scale lunar surface and near-lunar space exploration tasks can be completed, long-term lunar space environment monitoring is realized, and wide application prospects are achieved.

The invention discloses a method for the super-hydrophobic modification of glass cover plate surface. The method comprises the steps of conducting the laser etching and the subsequent hydroxylation to the glass cover plate surface after cleaning treatment of the surface, forming a nano coating on the glass cover plate surface, at last using the soaking method or the chemical vapor deposition to apply the modification of low surface energy materials on the glass cover plate surface. The method has the advantages of being simple in processing, having no requirement of special equipment, being simple to promote and implement, being good in repeatability and the like. What's more noteworthy is the glass cover plate modified by the method can resist multiple times of wiping, keep the super-hydrophobic self-cleaning property even after being subject to high heat and long time ultraviolet radiation, thus being suitable for the deep space exploration shuttles operating in disastrously dusty environment.

A design engine generates a spectrum of design options to solve an architectural design problem. When generating a given design option, the design engine processes a set of design objectives and design constraints to generate an initial design plan. The initial design plan defines generative regions where geometry can be created and non-generative regions where geometry creation is restricted. The design engine generates a set of pathways that divide the design plan into multiple parcels and then divides each parcel further to produce a collection of cells. The design engine selects specific cells for major programs and merges these cells with adjacent cells until program space requirements are met. The design engine distributes minor programs within the remaining unoccupied cells of the design plan, thereby producing the design option.

The present invention relates to a method of utilizing a 2D radar to realize space exploration. The method comprises the following steps of setting a 2D laser radar and a rotating part on a mobile main body; setting a power supply module, a main control module, a signal processing module and a driving module in the mobile main body, wherein the power supply module supplies a working voltage to the main control module, the 2D laser radar is connected with the rotating part, and the rotating part is connected with the main control module via the driving module; using the main control module to drive the rotating part to rotate up and down or left and right around the right side of the mobile main body via the driving module, using the rotating part to drive the 2D laser radar to rotate, and using the 2D laser radar to send a detected electromagnetic wave which is emitted back by a front barrier to the signal processing module; using the signal processing module to process the received electromagnetic wave and then send to the main control module, and using the main control module to calculate the orientation and distance information of the front barrier. According to the present invention, the 2D laser radar can be utilized to finish the omnibearing detection in front of the mobile main body.

The invention discloses a universal multi-sample scenario generation method. The universal multi-sample scenario generation method includes the steps of firstly, analyzing an initial scenario to generate a parametric scenario; secondly, selecting a factor set to establish a factor evaluation model so as to generate a scenario space; thirdly, generating a processing set so as to generate a multi-sample scenario; fourthly, generating multiple sample scenarios according to the multi-sample scenario. By the aid of the universal multi-sample scenario generation method, analysts only need to simulate generated samples by the aid of simulation software without spending a great amount of time in adjusting and designing factor level manually, so that scenario space exploration and analysis efficiency is improved remarkably. The invention further discloses a universal multi-sample scenario generation system achieved by the universal multi-sample scenario generation method.

The invention relates to a design method of a computer architecture structure, in particular to an ASIP architecture structure-oriented design method. The method mainly comprises the following steps of: firstly, selecting a typical open-source processor core, extracting system-level feature parameters after analyzing a specific application; determining specific values or forms to which the system-level feature parameters refer, and storing the system-level feature parameters into a feature parameter database; respectively establishing an ADL structure model and an ADL behavior model accordingto the feature parameters in the feature parameter database; and finally converting the established ADL models, verifying and optimizing the converted ADL models in third-party EDA environment, and logically and comprehensively downloading the ADL models into an SoC to be operated. The method follows a description-synthesis design methodology, and is capable of obtaining ASIP systems with the optimum comprehensive performance indexes through a chained process of application analysis-modeling description-design space exploration-synthesis-assessment-feedback.

The invention discloses a convolution acceleration method based on an FPGA. Firstly, a universal processor is used for analyzing neural network configuration information and weight data, writing the neural network configuration information and the weight data into a RAM, and aiming at external memory access bandwidth limitation and based on design space exploration, determining a cyclic partitioning factor to maximize data reuse, so that the operation performance of the whole network is improved. The FPGA reads configuration information from the RAM to generate an FPGA accelerator, the general processor reads picture information and writes the picture information into the DRAM, and the FPGA accelerator reads picture data from the DRAM, starts calculation and writes a calculation result into the DRAM. According to the accelerator, all the layers can be deployed on an FPGA chip at the same time and run in an assembly line mode, and the operation performance and the data throughput rate are improved.