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Design space parameter transfer learning method based on correlation and Gaussian process regression

A Gaussian process regression, design parameter technology, applied in complex mathematical operations, design optimization/simulation, special data processing applications, etc., can solve problems such as reduction, and achieve the effect of shortened time, time reduction, and effective trade-off

Pending Publication Date: 2021-05-25
SOUTHEAST UNIV
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Problems solved by technology

[0012] Technical problem: the technical problem to be solved by the present invention is the design space parameter transfer learning based on correlation and Gaussian process regression: correlate the correlation of PPA (performance, power consumption, area) target under different crafts, and pass Gaussian Copula as advanced technology Set prior information, use Gaussian process to predict the relationship between design parameters and PPA targets, adopt the method of estimation first and then verification, so as to select a small number of parameter designs to narrow the search space of design parameters, reduce time cost, and improve design speed

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  • Design space parameter transfer learning method based on correlation and Gaussian process regression
  • Design space parameter transfer learning method based on correlation and Gaussian process regression
  • Design space parameter transfer learning method based on correlation and Gaussian process regression

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Embodiment 1

[0095] The present invention will be described in detail below in conjunction with the accompanying drawings and examples.

[0096] Figure 5 Given the choice of design parameters in the simulation process, the parameters are designed as different values ​​and stored in the vector x, as shown in Table 2. After completing the logic synthesis and physical design, the corresponding PPA vector y will be generated i .

[0097] Table 2 parameter setting

[0098] Design Parameters x clock cycle 10 clock rising edge max 0.5 clock rising edge minimum 0.1 Clock Falling Edge Maximum 0.5 Clock falling edge minimum 0.1 build time 1 hold time 0.5

[0099] Target y under one process i , 1≤i≤N obey the same distribution, transform y through probability integral transformation i Converted to a random variable with a standard uniform distribution, ie U i =F(y i )~uniform(0,1) k , where F is y i Cumulative probability distribution...

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Abstract

The invention discloses a design space parameter transfer learning method based on correlation and Gaussian process regression, and the method comprises the steps: (1), reasonably fusing a correlation algorithm into design space exploration under different technologies, and associating the correlation of evaluation targets under different technologies; enabling the time of design space exploration under the advanced process to be greatly shortened, and effectively finding the optimal design under the advanced process through the optimal design under the previous process; (2), by utilizing the advantage that the output of Gaussian process regression is a mean value and a variance of a Gaussian process, fitting the Gaussian process by using data with correlation under each process, and effectively outputting probability distribution of design parameters under an advanced process and (3), obtaining optimal design parameters through Thompson sampling, and balancing the optimal design parameters of multiple targets. According to the method, the technology is applied to the EDA process, the time for searching the optimal design can be greatly shortened, and all targets can be effectively balanced.

Description

technical field [0001] The invention relates to a design space exploration technology, specifically design space parameter transfer learning based on correlation and Gaussian process regression, and belongs to the technical field of EDA design. Background technique [0002] With the development of semiconductor technology and the continuous reduction of process nodes, more and more devices or logic gates are integrated into one chip. According to Moore's law, as figure 1 As shown, by 2020, a chip will be able to integrate up to tens of billions of transistors. Such an integrated circuit with a large number of transistors brings great challenges to the electronic design automation (EDA) of the integrated circuit. [0003] Integrated circuit automation design is mainly divided into front-end design, logic synthesis, physical design and verification. Logic synthesis and physical design require engineers to specify or try various constraints and strategies to meet design requ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/20G06F17/18
CPCG06F30/20G06F17/18
Inventor 张萌张峥张倩茹胡突传
Owner SOUTHEAST UNIV
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