Nonvolatile semiconductor memory device and method for manufacturing the same
A non-volatile, memory device technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as open-circuit faults and increased contact resistance, and achieve the effect of suppressing defect conduction
Inactive Publication Date: 2015-03-18
KK TOSHIBA
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However, this method results in an open circuit fault between the active area and the contact and an increase in the contact resistance between the active area and the contact
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[0012] Various embodiments will be described below with reference to the accompanying drawings. In the following description, the same components are denoted by the same reference numerals, and descriptions of components already described are appropriately omitted.
[0013] figure 1 is a schematic plan view showing the nonvolatile semiconductor memory device according to the embodiment.
[0014] The nonvolatile semiconductor memory device 1 according to the embodiment includes a NAND flash memory. The nonvolatile semiconductor memory device 1 includes a semiconductor region 11 , a control gate electrode 60 , a selection gate electrode 65 , and a contact electrode 72 .
[0015] Such as figure 1 As shown, in the nonvolatile semiconductor memory device 1 , the plurality of semiconductor regions 11 extend, for example, in the X direction (first direction) and are arranged in the Y direction (second direction) crossing the X direction. The element isolation region 50 is provide...
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According to one embodiment, a nonvolatile semiconductor memory device includes semiconductor regions, an element isolation region, control gate electrodes, a floating gate layer, a first insulating film, a second insulating film, a select gate electrode, and a contact electrode. The element isolation region is provided between the semiconductor regions. The control gate electrodes are provided on the semiconductor regions. The floating gate layer is provided in a position where the semiconductor regions and the control gate electrodes cross. The first insulating film is provided between the floating gate layer and the semiconductor regions. The second insulating film is provided between the floating gate layer and the control gate electrodes. The select gate electrode is provided on the semiconductor regions. The contact electrode is disposed on an opposite side of the select gate electrode from the control gate electrodes, and is in contact with one of the semiconductor regions.
Description
[0001] Cross References to Related Applications [0002] This application is based upon and claims the benefit of priority from US Provisional Patent Application 61 / 875,752, filed September 10, 2013, which is hereby incorporated by reference in its entirety. technical field [0003] Embodiments described herein generally relate to nonvolatile semiconductor memory devices and methods of manufacturing the same. Background technique [0004] In a nonvolatile semiconductor memory device in which a plurality of NAND strings are arranged, the pitch between the NAND strings becomes narrower with miniaturization. As a result, the possibility of adjacent NAND strings being short-circuited through contacts connected to the active regions of the NAND strings gradually increases. [0005] In order to avoid such a short circuit phenomenon, there is a method of narrowing the width of a contact connected to an active region. However, this approach results in an open circuit fault between...
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IPC IPC(8): H01L27/115H01L23/50H01L21/8247H10B69/00
CPCH01L29/66825H01L29/788H10B41/35
Inventor 藤井光太郎
Owner KK TOSHIBA