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A time-domain deconvolution interleaving device and method suitable for DDR memory

A deconvolution and memory technology, applied in the field of time-domain deconvolution and interleaving devices, can solve problems such as reducing DDR efficiency, discontinuous addresses for reading and writing data, etc.

Active Publication Date: 2017-06-30
HAIER BEIJING IC DESIGN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Due to the different delays of each channel in deconvolution and interleaving, the addresses of each read and write data are not continuous, which will significantly reduce the efficiency of DDR

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  • A time-domain deconvolution interleaving device and method suitable for DDR memory
  • A time-domain deconvolution interleaving device and method suitable for DDR memory
  • A time-domain deconvolution interleaving device and method suitable for DDR memory

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Embodiment Construction

[0021] The method of the present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0022] The purpose of the present invention is to design a deconvolution interleaving device and method suitable for DDR storage, so as to improve DDR efficiency and save off-chip RAM. The deconvolution and interleaving device may also be called a deconvolution and interleaving module.

[0023] figure 1 It is a schematic diagram of the deconvolution interleaving device / module. As shown, the deconvolution interleaving module consists of two random access memory RAMs with dual read-write ports, one first-in-first-out memory FIFO with a depth of 4, and two logic controls Circuit composition. The logic control circuit can also be called a logic control unit. The two random access memory RAMs with dual read-write ports can be referred to as the first RAM and the second RAM respectively, or respectively: the first dual rea...

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Abstract

The present invention relates to a time-domain deconvolution and interleaving device and method suitable for DDR memory. The device includes two dual read-write RAMs, FIFOs, and two logic control circuits. The first logic control circuit is responsible for input data or output data Exchange with two RAMs; the second logic control circuit is responsible for data exchange between the two RAMs and the DDR interface, and in DDR, assign continuous physical address spaces for channels 0 to 50 respectively; when the first logic When the control circuit updates a group of data in the first RAM or the second RAM, the second logic control circuit puts the group of data into the corresponding physical address space of DDR, and reads the next group of data into the corresponding first RAM Or the second RAM; read / write one row continuously at a time, you can read one row and write one row alternately, or you can read all the rows before writing. The deconvolution and interleaving device and method suitable for DDR storage of the present invention multiplex DDR storage units, save off-chip RAM, and improve DDR efficiency.

Description

technical field [0001] The invention relates to the field of digital signal processing, in particular to a time-domain deconvolution and interleaving device and method suitable for DDR memory. Background technique [0002] In the prior art, in the digital television terrestrial broadcasting transmission system involving convolutional interleaving of symbols in the time domain, correspondingly, deconvolution and interleaving of the symbols is required at the receiving end. Deconvolution interleaving requires a relatively large storage space. In a typical case, the interleaving width B=52, the interleaving depth M=720, and a symbol requires 24 bits, which requires about 3 Mbits of storage space. [0003] A large storage space can use an external dedicated RAM (Random-Access Memory, random access memory), which increases the cost of the chip. The common DDR (Double Data Rate RAM) of the chip has a large storage space, and the deconvolution and interleaving device can use this ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06G06F12/0868G06F12/0871
Inventor 刘琦
Owner HAIER BEIJING IC DESIGN