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FinFet device source and drain region forming method

A technology for source and drain regions and devices, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, and electrical components. Effect

Active Publication Date: 2015-03-25
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, traditional large-angle implantation will be affected by the shadow effect brought about by the small pitch of Fin, resulting in uneven doping, and the doping concentration on the side of the fin is lower than that on the top.
Although plasma doping can achieve uniform doping, it may introduce other defects due to the inability to perform quality screening, which will affect the characteristics of the device

Method used

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  • FinFet device source and drain region forming method
  • FinFet device source and drain region forming method
  • FinFet device source and drain region forming method

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Embodiment Construction

[0021] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0022] A schematic diagram of a layer structure according to an embodiment of the invention is shown in the drawing. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, sizes, and relati...

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Abstract

The invention provides a FinFet device source and drain region forming method. The FinFet device source and drain region forming method comprises the steps of providing a substrate, wherein fins are arranged on the substrate; conducting ion implantation on the source and drain regions of the fins; covering the source and drain regions of the fins to form an interlayer layer, wherein the thickness of the interlayer layer at the tops of the fins is larger than that of the interlayer layer on the side faces of the fins; performing thermal annealing; removing the interlayer layer. Due to the dephlegmation effect of impurities on the fins and the interlayer layer, the impurities diffuse towards the interlayer layer, more impurities are dissolved out of the thicker position of the interlayer layer, and uniform conformal doping is achieved by removing the impurities dissolved out of the surfaces of the fins.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for ion implantation of a FinFet device. Background technique [0002] As the size of planar semiconductor devices continues to shrink, the short-channel effect becomes more and more prominent. Improving gate control capabilities has become a key direction in the development of next-generation devices. Similar to FinFet (fin field-effect transistor) multi-gate devices, FinFet is a multi-gate device with A transistor with a fin-type channel structure, which uses several surfaces of a thin fin (Fin) as a channel, can increase the operating current, thereby preventing the short-channel effect in traditional transistors. [0003] In the actual manufacturing process of FinFet devices, an important challenge is the preparation of FinFET source and drain doped regions. In planar devices, ions are directly implanted on the surface of planar devices, and activated by an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/265
CPCH01L21/265H01L29/0847H01L29/66795
Inventor 刘金彪徐强熊文娟李春龙李俊峰刘青王垚
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI