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Die and Chip

A bare die, lateral edge technology used in semiconductor/solid state device components, semiconductor devices, electrical components, etc. to address issues such as increased risk of contact pad contamination

Inactive Publication Date: 2018-10-16
INFINEON TECH AUSTRIA AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the risk of unwanted contamination of the contact pads tends to increase

Method used

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Embodiment Construction

[0017] Hereinafter, embodiments according to the present invention will be described in more detail. In this context, generalized reference signs will be used to describe several objects at the same time, or to describe common features, dimensions, characteristics, etc. of these objects. General reference symbols are based on their specific reference symbols. Furthermore, objects that appear in several embodiments or several drawings but are the same or at least similar in terms of at least some of their functions or structural features will be indicated with the same or similar reference symbols. In order to avoid unnecessary repetition, parts of the description referring to such objects will also refer to corresponding objects in different embodiments or in different drawings, unless otherwise expressly or implicitly indicated in consideration of the context of the description and drawings. Thus, similar or related objects can be realized with at least some of the same or s...

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PUM

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Abstract

Various embodiments of the invention relate to dies and chips. A die according to an embodiment includes: contact pads configured to provide electrical contact to circuit elements included in the die; lateral edges proximate to the contact pads; and a cover layer including a protective structure, the protective structure includes at least one elongated structure, wherein the cover layer includes an opening providing access to the contact pad, so as to electrically couple the contact pad with an external contact, wherein the protective structure is arranged at the lateral edge and the contact pad between. By using embodiments, the risk of contamination to the top side of the die can be reduced during fabrication and packaging of the chip.

Description

technical field [0001] Various embodiments of the invention relate to dies and chips. Background technique [0002] Today, electronic and electrical devices, including integrated circuits (ICs), sensors, and other more complex devices, but also discrete electronic devices, are often implemented based on thin film and semiconductor or semiconductor-related technologies. Corresponding structures are typically formed on or integrated into a substrate material such as a semiconductor material. The fabrication process is typically performed at the wafer level, which is then diced into individual die. The die are then typically packaged to form a chip. [0003] In a package frame, the die is typically mounted to a carrier such as a lead frame. Typically, the die is mounted to the carrier using some form of adhesive including solder paste. [0004] Often, however, these adhesives include some form of flux or other components that tend to creep onto the top surface of the die. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31
CPCH01L2924/13091H01L23/3121H01L23/3157H01L2924/181H01L2224/02245H01L24/29H01L24/32H01L24/48H01L24/73H01L24/83H01L24/85H01L24/92H01L2224/04042H01L2224/05624H01L2224/26145H01L2224/293H01L2224/29311H01L2224/29316H01L2224/32245H01L2224/48245H01L2224/48463H01L2224/73265H01L2224/83801H01L2224/92247H01L2924/00014H01L2224/29294H01L2224/48091H01L2224/48247H01L2224/05553H01L24/05H01L2924/00H01L2924/014H01L2924/01014H01L2924/01029H01L2224/45099H01L23/48H01L23/564
Inventor B·克尼普费尔
Owner INFINEON TECH AUSTRIA AG