Memory rank margin test method combined with temperature and voltage variables

Abstract

The invention particularly relates to a memory rank margin test method combined with temperature and voltage variables. According to the memory rank margin test method, the rank margin test and temperature and Vdd four corner test are combined together, and the rank margin test is carried out under the condition of biasing temperature and Vdd voltage. Through contrast verification, the memory rank margin test method can more eliminate 70 percent of leakage problems by adding the rank margin test of the temperature and Vdd corner angle test. The method can simulate whether the problems exist in rank margin or not in the practical application under the condition with bad environment temperature and voltage, also can find a lot of problems of power, SI and layout on the memory support aspect.

Description

technical field [0001] The invention relates to the technical field of computer testing, in particular to a memory rank margin testing method combined with temperature and voltage variables. Background technique [0002] At present, the memory rank margin test is a kind of memory test scheme under normal temperature and normal voltage. The whole test scheme is embedded in a specific BIOS. Enable the Rank Margin Tool option in the BIOS, and the platform will automatically enter the Rank Margin test mode. , the test result is output by the serial port. Rank margin test is the most concise and intuitive test method for signal integrity, which can detect the margin of the motherboard to the memory design. However, judging from the actual measurement results, it is rare to exceed the spec. The judgment criteria are relatively loose, which is too easy for the design to pass, and some design bugs are often leaked from the effect point of view. [0003] The following is a detaile...

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Problems solved by technology

However, under low voltage, the driving ability of particles, that is, the slew rate, is reduced, and the setup time and hold time of the signal are prone to be insufficient.