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Forming method of semiconductor device

A semiconductor and device technology, which is applied in the field of semiconductor device formation and can solve problems such as affecting the performance of semiconductor devices.

Active Publication Date: 2015-07-01
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] However, in the actual process, after forming the stress layer of the PMOS gate and the NMOS gate, it is found that the structure of the PMOS dummy gate 20 and the NMOS dummy gate 30 is destroyed, which directly affects the subsequent connection with the PMOS dummy gate 20 and the NMOS dummy gate 20 and the NMOS dummy gate. The structure of the gate 30 matches the structure of the PMOS gate and the NMOS gate, thereby affecting the performance of the subsequently formed semiconductor device

Method used

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  • Forming method of semiconductor device

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Embodiment Construction

[0040] As mentioned in the background, in the existing embedded stress transistor manufacturing process, it is easy to cause damage to the PMOS dummy gate and the NMOS dummy gate, thereby affecting the subsequently formed PMOS gate and NMOS gate structures.

[0041] Analyze the cause of damage to the PMOS dummy gate and NMOS dummy gate, refer to image 3 As shown, in the manufacturing process of the embedded stress transistor, after the dummy gate material layer is formed on the semiconductor substrate, the first hard mask layer used to form the dummy gate, and subsequently cover the PMOS in the process of forming the compressive stress layer Both the dummy gate 20 and the second hard mask material layer 41 on the NMOS dummy gate 30 are SiN. After forming the compressive stress layers 51 on both sides of the PMOS dummy gate 20, removing the second hard mask layer 41 covering the NMOS dummy gate 30, and covering the first hard mask layer on the PMOS dummy gate 20 21 were remov...

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Abstract

The invention discloses a forming method of a semiconductor device. After a pseudo gate material layer is formed on a semiconductor substrate, a first mask layer is formed on the pseudo gate material layer, then after the first hard mask layer and the pseudo gate material layer are etched to form a pseudo gate structure, the first hard mask layer is reserved on the pseudo gate structure, in a later embedded stress transistor preparation technology, the first hard mask layer always covers the pseudo gate, and thereby the pseudo gate structure is prevented from being damaged, and then a metal grate structure matched with the pseudo gate structure formed subsequently is ensured.

Description

technical field [0001] The invention relates to the field of semiconductor formation, in particular to a method for forming a semiconductor device. Background technique [0002] In VLSI, strained silicon technology (Strained Silicon) is usually used to form tensile stress on NMOS transistors and compressive stress on PMOS transistors, thereby increasing the carrier mobility of NMOS transistors and PMOS transistors, increasing the Drive current to improve the response speed of the circuit. Embedded stress transistor is one of the hotspots in the application of strained silicon technology. [0003] Based on the structure of the compressive stress layer of PMOS and the tensile stress layer of NMOS in the embedded stress transistor, and the materials used are different, the compressive stress layer of PMOS and the tensile stress layer of NMOS are prepared step by step. Taking the process of forming a compressive stress layer first and then forming a tensile stress layer as an ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/8238
CPCH01L21/28008H01L29/66545
Inventor 毛刚
Owner SEMICON MFG INT (SHANGHAI) CORP