Memory device and memory control method

Abstract

A memory device and memory control method, the memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines. The column decoder includes a plurality of even channel transistors, a plurality of even clamp transistors, a plurality of odd channel transistors, and a plurality of odd clamp transistors. The control terminal of each even-clamp transistor is coupled to an even-clamp line, the first end of each even-clamp transistor is respectively coupled to a single one of the even-local bit lines, and each even-clamp transistor's Both the second ends are coupled to a ground potential. The control terminal of each odd clamp transistor is coupled to an odd clamp line, the first terminal of each odd clamp transistor is coupled to a single one of the odd local bit lines, and the odd clamp transistor's Both the second ends are coupled to the ground potential. The invention can effectively eliminate the capacitive coupling effect between adjacent storage units.

Description

technical field [0001] The present invention relates to a memory device, in particular to a memory device with a column decoder, wherein the column decoder can be used to reduce the capacitive coupling effect (Capacitive Coupling Effect) between adjacent memory cells. Background technique [0002] figure 1 is a schematic diagram showing a conventional memory device 100 . Such as figure 1 As shown, the memory device 100 includes at least a memory cell array (Memory Cell Array) 110 and a column decoder (Column Decoder) 120 . To simplify the drawing, the remaining elements of the memory device 100 are omitted and not shown in figure 1 middle. The memory cell array 110 includes a plurality of memory cells (Memory Cell). A plurality of word lines (Word Line) WL and a plurality of local bit lines (Local Bit Line) BL can be used to select these memory cells. In addition, the column decoder 120 can be used to selectively couple one of the local bit lines BL to a global bit lin...

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a memory device and a memory control method to solve the serious mutual coupling phenomenon between transistors caused by the influence of parasitic capacitance between adjacent cells

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