Memorizer apparatus and memorizer control method

Abstract

The invention discloses a memorizer apparatus and a memorizer control method. The memorizer apparatus comprises a memory cell array and a column decoder; the memory cell array comprise a plurality of even local bit lines, and a plurality of odd local bit lines; the column decoder comprises a plurality of even channel transistors, a plurality of even clamped transistors, a plurality of odd channel transistors, and a plurality of odd clamped transistors; the control terminal of each even clamped transistor is connected with an even clamped wire via coupling connection; the first terminal of each even clamped transistor is connected with one independent even local bit line via coupling connection; the second terminal of each even clamped transistor is connected with a ground potential via coupling connection; the control terminal of each odd clamped transistor is connected with an odd clamped wire via coupling connection; the first terminal of each odd clamped transistor is connected with one independent odd local bit line via coupling connection; and the second terminal of each odd clamped transistor is connected with the ground potential via coupling connection. The memorizer apparatus is capable of eliminating capacitive coupling effect between adjacent memory cells effectively.

Description

technical field [0001] The present invention relates to a memory device, in particular to a memory device with a column decoder, wherein the column decoder can be used to reduce the capacitive coupling effect between adjacent memory cells. Background technique [0002] figure 1 is a schematic diagram showing a conventional memory device 100 . Such as figure 1 As shown, the memory device 100 includes at least a memory cell array (Memory Cell Array) 110 and a column decoder (Column Decoder) 120 . To simplify the drawing, the remaining elements of the memory device 100 are omitted and not shown in figure 1 middle. The memory cell array 110 includes a plurality of memory cells (Memory Cell). A plurality of word lines (Word Line) WL and a plurality of local bit lines (Local Bit Line) BL can be used to select these memory cells. In addition, the column decoder 120 can be used to selectively couple one of the local bit lines BL to a global bit line (Global Bit Line) GBL. [...

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a memory device and a memory control method to solve the serious mutual coupling phenomenon between transistors caused by the influence of parasitic capacitance between adjacent cells

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