Manufacturing method of semiconductor memory device

Abstract

The invention relates to a manufacturing method of a semiconductor memory. The manufacturing method includes: forming a plurality of bit line structures on a semiconductor substrate, the bit line structures extending along a first direction and repeatedly arranged in a second direction; forming barriers on the semiconductor substrate on which the bit line structures are formed layer, the barrier layer covers the semiconductor substrate and a plurality of bit line structures; forms a layer of sacrificial material filling the grooves between the bit line structures; forms a hard mask pattern, and uses the hard mask pattern as a mask plate to sacrificially The material layer is etched to form a plurality of strip-shaped sacrificial spacers extending along the second direction; a first protective spacer is formed on the sidewall of the sacrificial spacer, and the first protective spacer and the bit line structure jointly define a Capacitive contact window; removing the sacrificial spacer, forming an air gap between two first protective spacers corresponding to the same sacrificial spacer, and forming a sealing layer on top of the air gap.

Description

technical field [0001] The present invention relates to the technical field of semiconductor storage devices, and in particular, to a manufacturing method of a semiconductor storage device. Background technique [0002] One of the development trends of DRAM (dynamic Random Access Memory, dynamic random access memory) is to achieve the purpose of producing more chips on a wafer by shrinking the process and reducing the size of devices such as transistors. However, as the size becomes smaller and smaller, the parasitic capacitance between adjacent metal wires increases, which will lead to the read delay of the DRAM internal signal, the strength will be weakened, and more seriously, it will lead to low yield or even zero good quality of the chip. Effectively reducing parasitic capacitance has become an important issue in advanced semiconductor manufacturing processes. [0003] At present, the commonly used DRAM bit line structure often adopts a stacked structure. Silicon nitri...

AI Technical Summary

Problems solved by technology

[0004] Based on this, it is necessary to provide a semiconductor storage device manufacturing method for the problem of complex process flow when forming a capacitive contact window

Images