A kind of manufacturing method of mos transistor

Abstract

The invention provides a method for manufacturing a MOS transistor, comprising: a. providing a semiconductor substrate, dummy gate stacks, spacers, and source-drain regions; b. forming a first interlayer dielectric layer whose height is less than that of the dummy gate The height of the stack; c. remove the part of the first interlayer dielectric layer located at both ends away from the dummy gate stack to form a first vacancy; d. fill the second interlayer dielectric layer in the first vacancy, which The top is located between the top of the first interlayer dielectric layer and the top of the gate stack; e. forming a third interlayer dielectric layer to cover the first interlayer dielectric layer and the second interlayer dielectric layer; f. forming a through hole exposing the first interlayer dielectric layer in the interlayer dielectric layer; g. removing the first interlayer dielectric layer through the through hole to form a second vacancy; h. forming a cap layer to fill the through hole hole. The invention effectively reduces the gate parasitic capacitance and improves device performance.

Description

technical field [0001] The present invention relates to a semiconductor device structure and a manufacturing method thereof, in particular to a MOS transistor structure and a manufacturing method thereof. Background technique [0002] In the MOSFET structure, the gate parasitic capacitance is a key factor affecting the frequency response and switching speed of the device, and determines the gate RC delay and RF frequency response. In order to improve the performance of the device, we need to reduce the parasitic capacitance of the MOSFET as much as possible. As the size of the device decreases, the influence of the parasitic capacitance becomes more and more significant. Further reducing the parasitic capacitance of the device can significantly improve the performance of the device. [0003] Parasitic capacitance is directly determined by the physical structure of the device, and its size is directly related to the size of the device. Such as figure 1 As shown, the gate pa...

AI Technical Summary

Problems solved by technology

Due to many restrictions, for a device of a specific size, the gate length and gate height cannot be further reduced, and the change of the device structure will also cause many other negative effects, and the parasitic capacitance of the device is difficult to be further reduced

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