Shape-based memory test method and test circuit

Abstract

The invention provides a shape-based memory testing method, which judges the boundary storage area and intermediate storage area based on the physical shape of the memory, and simultaneously generates a test stimulus file, an expected test response file, and a mapping relationship table between stimulus and physical position and sends them to the chip The memory test circuit of the test is tested, and the test stimulus file makes the test intensity of the boundary storage area higher than the test intensity of the intermediate storage area; during the test, the read data is compared with the expected value of the expected test response file, and if they are consistent, the test pass, if inconsistent, then the test fails, and then the test result is sent to the outside of the chip, and when the test result is a test failure, read the content of the incentive and physical position mapping relationship file to obtain the physical position corresponding to the current address, and Send the physical location information of the defect out of the chip. In this way, the probability of detecting a defective chip in the storage unit is improved, and the physical position of the specific bit where the defect occurs is obtained through feedback.

Description

technical field [0001] The invention relates to a memory testing method and testing circuit based on shape. Background technique [0002] The memory unit is an important part of the SOC chip. If the memory unit is defective during the production process, it will affect the normal use of the entire chip. Due to the high complexity of its design, the memory unit is usually the most prone to defects in the entire chip. The circuit part. Therefore, the current common practice is to add a BIST (buildin selftest, self-built internal test) circuit in the chip design stage, and then use the BIST circuit to test the internal memory after the chip production is completed, and output the test results. Chips with defective memory cells are screened out. [0003] But the current BIST circuit has a problem, that is, it does not make corresponding key tests according to the actual physical shape of the memory, but tests all the bits in the memory cells with the same intensity. Since each...

AI Technical Summary

Problems solved by technology

Since each test algorithm has its test intensity, it is used to find different types of defects, but the algorithm with stronger test intensity (such as performing multiple read and write operations on the same address with different types of data, through different types of device flip actions to detect Covering different types of memory device defects) corresponds to a longer test time, so for the sake of test cost considerations, when using the same algorithm for all bits in the memory unit, only a test algorithm with moderate strength can be selected, which makes it impossible Cover all types of defect types, resulting in some bad films cannot be screened out

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