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Data to Cache Hierarchy Opportunistic Cache Injection in Low Latency Tier

A technology of high-speed buffering and data injection, which is used in electrical digital data processing, instrumentation, computing, etc., and can solve problems such as low memory levels.

Active Publication Date: 2020-05-19
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, other systems may have more or less memory levels

Method used

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  • Data to Cache Hierarchy Opportunistic Cache Injection in Low Latency Tier
  • Data to Cache Hierarchy Opportunistic Cache Injection in Low Latency Tier
  • Data to Cache Hierarchy Opportunistic Cache Injection in Low Latency Tier

Examples

Experimental program
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Embodiment Construction

[0019] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. However, the disclosed subject matter may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosed subject matter to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

[0020] It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer. to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on...

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PUM

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Abstract

According to one general aspect, a method may include receiving a request from a non-CPU device configured to perform direct memory access to write data within a memory system at a memory address. The method may further include determining, based on the memory address, whether to generate a cache tag hit through a cache level of a memory system that is closer in latency order to the central processor than a coherent memory interconnect. The method may further include injecting data into the cache level if the cache level generates a cache tag hit.

Description

[0001] Cross References to Related Applications [0002] This application requests the title "METHOD FOR OPPORTUNISTIC CACHE INJECTION OF DATA INTO LOWER LATENCY LEVELS OF THE CACHE HIERARCHY TO IMPROVEPERFORMANCE WHERE AN UNINTELLIGENT I / O DEVICE OR DMA MASTER UNISTIC CACHE INJECTION OF DATA INTO LOWER LATENCY LEVELS OF THE CACHE HIERARCHY TO IMPROVEPERFORMANCE WHERE AN UNINTELLIGENT I / O DEVICE OR DMA MASTER UNISTIC PRODUCES DATA TOBE CONSUMED RY CPU CORE (opportunistic cache injection of data into lower latency levels of the cache hierarchy to improve performance of dumb I / O devices or DMA masters producing data to be consumed by software running on CPU cores) "Provisional Patent Application Serial No. 61 / 969,077 of priority. The subject matter of this earlier filed application is hereby incorporated by reference. technical field [0003] This description relates to memory management, and more specifically, to a portion of memory associated with a portion of cacheable memor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0893G06F13/16
Inventor A.J.拉欣K.M.莱帕克
Owner SAMSUNG ELECTRONICS CO LTD