High-performance FinFETs

Abstract

A FinFET is described having first, second, and third pluralities of fins with gate structures and source and drain regions formed on the fins so that PMOS transistors are formed on the first plurality of fins, NMOS transistors are formed on the second plurality and PMOS transistors are formed on the third plurality. In one embodiment, the first and second pluralities of fins are made of strained silicon; and the third plurality of fins is made of a material such as germanium or silicon germanium that has a higher hole mobility than strained silicon. In a second embodiment, the first plurality of fins is made of silicon, the second plurality of strained silicon, germanium or a III-V compound; and the third plurality is made of germanium or silicon germanium.

Description

technical field [0001] The present application relates to semiconductor devices such as FinFETs (Fin Field Effect Transistors) (a / k / a Tri-Gate Transistors). Background technique [0002] A conventional field effect transistor (FET) is a substantially planar device with a gate structure extending across the surface of a semiconductor such as single crystal silicon, and doped source and drain regions in the semiconductor on either side of the gate Area. The gate is insulated from the semiconductor by a thin layer of insulator such as silicon oxide. A voltage applied to the gate controls current flow in an undoped channel in the semiconductor below the gate extending between the doped source and drain regions. [0003] The switching speed of a FET depends on the amount of current flowing between the source and drain regions. Current flow depends on the width of the gate, where width is the direction in the channel perpendicular to the direction of current flow. With the con...

AI Technical Summary

Problems solved by technology

This is especially troublesome in circuits that use a large number of PMOS transistors, such as static random access memory (SRAM) circuits

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